Convolutional interleaver/de-interleaver

Claim 3

The apparatus of claim 1, wherein the logic to provide the parameter M includes a store coupled to the address generator which stores a value indicating the parameter specifying the depth M.

Claim 4

The apparatus of claim 1, wherein the logic to provide the parameter I includes a store coupled to the address generator which stores a value indicating the parameter I.

Claim 5

The apparatus of claim 1, wherein the logic to provide the parameters M and I includes a store coupled to the address generator which stores values indicating the parameters M and I.

Claim 6

The apparatus of claim 1, wherein the logic to provide the parameters M and I includes a programmable store coupled to the address generator which stores values indicating at least one of the parameters M and I.

Claim 7

The apparatus of claim 1, wherein the convolutional pattern comprises a convolutional interleaving pattern.

Claim 8

The apparatus of claim 1, wherein the convolutional pattern comprises a convolutional de-interleaving pattern.

Claim 9

The apparatus of claim 1, wherein the address generator includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of a set defined as (1, 2, . . . ,I), and wherein the convolutional pattern comprises a convolutional interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(ICNT(t)+1)+X(t))+MCNT(t), where the factor X(t) is defined by X(t)=ICNT(t)+X(t-1), and X(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.

Claim 10

The apparatus of claim 1, wherein the address generator includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to a common multiple of set defined as (1, 2, . . . ,I), and wherein the convolutional pattern comprises a convolutional de-interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR as follows: ADDR=M(BCNT(t)mod(I-ICNT(t))+Y(t))+MCNT(t), where the factor Y(t) is defined by Y(t)=Z(t-1), and Z(t)=(I-ICNT(t)+Z(t-1)), and Z(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I, and is enabled when (I-ICNT(t)) is less than I.

Claim 11

The apparatus of claim 8, wherein the common multiple consists of the least common multiple.

Claim 12

The apparatus of claim 9, wherein the common multiple consists of the least common multiple.

Claim 13

The apparatus of claim 1, including logic, having an interleave state and a de-interleave state, to operate the address generator according to a convolutional interleaving function in the interleave state and according to a convolutional de-interleaving function in the de-interleave state.

Claim 14

The apparatus of claim 12, wherein the address generator includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to a common multiple of a set defined as (1, 2, . . . , I), and wherein in the interleave state the convolutional pattern comprises a convolutional interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M*(BCNT(t)mod(ICNT(t)+1)+X(t))+MCNT(t), where the factor X(t) is defined by X(t)=ICNT(t)+X(t-1), and X(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I; in the de-interleave state, the convolutional pattern comprises a convolutional de-interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M*(BCNT(t)mod(I-ICNT(t)))+Y(t)+MCNT(t), where the factor Y(t) is defined by Y(t)=Z(t-1), and Z(t)=(I-ICNT(t))+Z(t-1)), and Z(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I, and is enabled when (I-ICNT(t)) is less than I.

Claim 15

The apparatus of claim 13, wherein the common multiple consists of the least common multiple.

Claim 16

A communication channel processor, comprising: a packet input receiving a stream of error protected packets of data in time with a clock, the error protected packets including units of data; a coder output; a memory having an address input, a data input coupled to the packet input and a data output coupled to the coder output; and an address generator, coupled with the clock, which supplies a sequence of addresses to the address input in time with the clock, according to a convolutional pattern having cells having a depth equal to M units of data and having a number of rows I+1, and each row including i cells based on an index i going from 0 to I, and including logic, having an interleave state and a de-interleave state, to operate the address generator according to a convolutional interleaving function in the interleave state and according to a convolutional de-interleaving function in the de-interleave state.

Claim 17

A communication channel processor, comprising: a packet input receiving a stream of error protected packets of data in time with a clock, the error protected packets including units of data; a coder output; a memory having an address input, a data input coupled to the packet input and a data output coupled to the coder output; and an address generator, coupled with the clock, which supplies a sequence of addresses to the address input in time with the clock, according to a convolutional pattern having cells having a depth equal to M units of data and having a number of rows I+1, and each row including i cells based on an index i going from 0 to I, and including logic, having an interleave state and a de-interleave state, to operate the address generator according to a convolutional interleaving function in the interleave state and according to a convolutional de-interleaving function in the de-interleave state.

Claim 18

The communication channel processor of claim 15, including programmable memory coupled to the address generator which stores a value indicating the depth M, and logic responsive to the stored value to generate the sequence of addresses.

Claim 19

The communication channel processor of claim 15, including programmable memory coupled to the address generator which stores a value indicating the number of rows, and logic responsive to the stored value to generate the sequence of addresses.

Claim 20

The communication channel processor of claim 15, including programmable memory coupled to the address generator which stores a value indicating the number of rows, and a value indicating the depth M, and logic responsive to the stored values to generate the sequence of addresses.

Claim 21

The communication channel processor of claim 15, wherein the convolutional pattern comprises a convolutional interleaving pattern, and including: a channel input receiving a stream of channel data; and an outer encoder, connected between the channel input and the packet input, to encode a stream of channel data to generate the stream of error protected packets.

Claim 22

The communication channel processor of claim 19, wherein the outer encoder comprises a Reed-Solomon encoder.

Claim 23

The communication channel processor of claim 15, wherein the convolutional pattern comprises a convolutional de-interleaving pattern, and including: a channel output; and an outer decoder, connected between the data output of the memory and the channel output, to decode the stream of packet of error protected packets.

Claim 24

The communication channel processor of claim 21, wherein the outer decoder comprises a Reed-Solomon decoder.

Claim 25

The communication channel processor of claim 15, wherein the address generator includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of set defined as (1, 2, . . . ,I), and wherein the convolutional pattern in the interleave state comprises a convolutional interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(ICNT(t)+1)+X(t))+MCNT(t), where the factor X(t) is defined by X(t)=ICNT(t)+X(t-1), and X(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.

Claim 26

The communication channel processor of claim 15, wherein the address generator includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of set defined as (1, 2, . . . ,I), and wherein the convolutional pattern in the de-interleave state comprises a convolutional de-interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(I-ICNT(t))+Y(t))+MCNT(t), where the factor Y(t) is defined by Y(t)=Z(t-1), and Z(t)=(I-ICNT(t))+Z(t-1)), and Z(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.

Claim 27

The communication channel processor of claim 23, wherein the common multiplier consists of the least common multiplier.

Claim 28

The communication channel processor of claim 24, wherein the common multiple consists of the least common multiple.

Claim 29

The communication channel processor of claim 15, wherein the address generator includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to a common multiple of a set defined as (1, 2, . . . , I), and wherein in the interleave state the convolutional pattern comprises a convolutional interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M*(BCNT(t)mod(ICNT(t)+1)+X(t))+MCNT(t), where the factor X(t) is defined by X(t)=ICNT(t)+X(t-1), and X(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I; in the de-interleave state, the convolutional pattern comprises a convolutional de-interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M*(BCNT(t)mod(I-ICNT(t)))+Y(t)+MCNT(t), where the factor Y(t) is defined by Y(t)=Z(t-1), and Z(t)=(I-ICNT(t))+Z(t-1)), and Z(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I, and is enabled when (I-ICNT(t)) is less than I.

Claim 30

The communication channel processor of claim 27, wherein the common multiple consists of the least common multiple.

Claim 31

A communication channel processor, comprising: a channel input receiving a stream of channel data; and a Reed-Solomon encoder, having an input coupled to the channel input, and having an encoder output, to encode the stream of channel data to generate a stream of error protected packets; a channel output; a memory having an address input, a data input coupled to the encoder output and a data output coupled to the channel output, and supporting read-modify-write operations in time with the clock, the read-modify-write operations operating at a memory location identified by an address on the address input to supply a unit of data read from the memory location to the data output, and supply a unit of data from the data input to the memory location; an address generator, coupled with the clock, which supplies a sequence of addresses to the address input in time with the clock, according to a convolutional pattern having cells having a depth equal to M units of data and having a number of rows I+1, and each row including i cells based on an index i going from 0 to I; programmable memory coupled to the address generator which stores a value specifying the number of rows, and a value specifying the depth M, and logic responsive to the stored values to generate the sequence of addresses; and wherein the logic responsive to the stored values includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of a set defined as (1, 2, . . . , I), and wherein the convolutional pattern comprises a convolutional interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(ICNT(t)+1)+X(t))+MCNT(t), where the factor X(t) is defined by X(t)=ICNT(t)+X(t-1), and X(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.

Claim 32

A communication channel processor, comprising: a channel input receiving a stream of channel data; and a Reed-Solomon encoder, having an input coupled to the channel input, and having an encoder output, to encode the stream of channel data to generate a stream of error protected packets; a channel output; a memory having an address input, a data input coupled to the encoder output and a data output coupled to the channel output, and supporting read-modify-write operations in time with the clock, the read-modify-write operations operating at a memory location identified by an address on the address input to supply a unit of data read from the memory location to the data output, and supply a unit of data from the data input to the memory location; an address generator, coupled with the clock, which supplies a sequence of addresses to the address input in time with the clock, according to a convolutional pattern having cells having a depth equal to M units of data and having a number of rows I+1, and each row including i cells based on an index i going from 0 to I; programmable memory coupled to the address generator which stores a value specifying the number of rows, and a value specifying the depth M, and logic responsive to the stored values to generate the sequence of addresses; and wherein the logic responsive to the stored values includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of a set defined as (1, 2, . . . , I), and wherein the convolutional pattern comprises a convolutional interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(ICNT(t)+1)+X(t))+MCNT(t), where the factor X(t) is defined by X(t)=ICNT(t)+X(t-1), and X(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.

Claim 33

A communication channel processor, comprising: a channel input receiving a stream of channel data including error protected packets; and a channel output; a memory having an address input, a data input coupled to the encoder output and a data output coupled to the channel output, and supporting read-modify-write operations in time with the clock, the read-modify-write operations operating at a memory location identified by an address on the address input to supply a unit of data read from the memory location to the data output, and supply a unit of data from the data input to the memory location; a Reed-Solomon decoder, having an input coupled to the data output of the memory, and having an decoder output coupled to the channel output, to decode the stream of error protected packets to recover channel data; an address generator, coupled with the clock, which supplies a sequence of addresses to the address input in time with the clock, according to a convolutional pattern having cells having a depth equal to M units of data and having a number of rows I+1, and each row including i cells based on an index i going from 0 to I; programmable memory coupled to the address generator which stores a value specifying the number of rows, and a value specifying the depth M, and logic responsive to the stored values to generate the sequence of addresses; and wherein the logic responsive to the stored values includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of a set defined as (1, 2, . . . , I), and wherein the convolutional pattern comprises a convolutional de-interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(I-ICNT(t))+Y(t))+MCNT(t), where the factor Y(t) is defined by Y(t)=Z(t-1), and Z(t)=(I-ICNT(t))+Z(t-1)), and Z(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.

Claim 34

A communication channel processor, comprising: a channel input receiving a stream of channel data including error protected packets; and a channel output; a memory having an address input, a data input coupled to the encoder output and a data output coupled to the channel output, and supporting read-modify-write operations in time with the clock, the read-modify-write operations operating at a memory location identified by an address on the address input to supply a unit of data read from the memory location to the data output, and supply a unit of data from the data input to the memory location; a Reed-Solomon decoder, having an input coupled to the data output of the memory, and having an decoder output coupled to the channel output, to decode the stream of error protected packets to recover channel data; an address generator, coupled with the clock, which supplies a sequence of addresses to the address input in time with the clock, according to a convolutional pattern having cells having a depth equal to M units of data and having a number of rows I+1, and each row including i cells based on an index i going from 0 to I; programmable memory coupled to the address generator which stores a value specifying the number of rows, and a value specifying the depth M, and logic responsive to the stored values to generate the sequence of addresses; and wherein the logic responsive to the stored values includes a first counter producing a value ICNT(t) which increments in response to the clock when a new unit a data is to be processed and resets in response to the clock when ICNT(t) reaches I, a second counter producing a value MCNT(t) which increments in response to the clock when ICNT(t) is equal to I, and resets in response to the clock when MCNT(t) reaches M-1, a third counter which produces a value BCNT(t) which increments in response to the clock when MCNT(t) is equal to M-1, and resets in response to the clock when BCNT(t) reaches B-1, where B is equal to the least common multiple of a set defined as (1, 2, . . . , I), and wherein the convolutional pattern comprises a convolutional de-interleaving pattern, and the sequence of addresses is computed according to a formula for a current address ADDR logically equivalent to the following: ADDR=M(BCNT(t)mod(I-ICNT(t))+Y(t))+MCNT(t), where the factor Y(t) is defined by Y(t)=Z(t-1), and Z(t)=(I-ICNT(t))+Z(t-1)), and Z(t-1) is reset to zero in response to the clock when the value ICNT(t) equals I.