US5915104A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High bandwidth PCI to packet switched router bridge having minimized memory latency
Assignee: Morgan Stanley and Co LLC
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Filing: 1997-01-09
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Granted: 1999-06-22
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Expires: 2017-01-09
Abstract
Abstract In a computer system, a mechanism for minimizing memory latencies. An improved, high-speed packet switched router is used to route packets quickly and efficiently between the microprocessor and the main memory. The computer system also supports PCI devices by implementing a bridge which acts as an interface between the PCI bus and the packet switched router. In order to minimize the memory latencies for PCI based memory accesses through the bridge, a plurality of read and write buffers are implemented. Write gathering is used to gather a plurality of write transactions on the PCI bus into the write buffers and sent by the bridge as one cache line sized transfer to the routing mechanism. For PCI based read operations, data is pre-fetched from the main memory and stored in the read buffers. Thereby, PCI devices can access the read buffers multiple times to retrieve the requested data.
Inventors
- 👤 Steven C. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
196 words
A computer system comprising: a routing mechanism for routing packets of data; a processor coupled to the routing mechanism for processing the data; a memory coupled to the routing mechanism for storing the data; a PCI bus for conveying PCI format data; a PCI device coupled to the PCI bus; a bridge coupled between the routing mechanism and the PCI bus for providing an interface between the PCI bus and the routing mechanism; a plurality of write buffers coupled to the bridge, wherein a plurality of write transactions on the PCI bus are combined into one cache line sized transfer to the routing mechanism; a plurality of read buffers coupled to the bridge, wherein data fetched according to a read request from the device is stored in the read buffers and the device can access the read buffer multiple times to retrieve the data; a prefetcher coupled to the bridge, wherein when the PCI device generates a read request and there is no corresponding data contained in the read buffers, the bridge reads sequential cache lines until the read buffers are full, a page boundary is encountered, or the read buffers are caused to be flushed.
Claim 2
Dependent Claim
196 words
A computer system comprising: a routing mechanism for routing packets of data; a processor coupled to the routing mechanism for processing the data; a memory coupled to the routing mechanism for storing the data; a PCI bus for conveying PCI format data; a PCI device coupled to the PCI bus; a bridge coupled between the routing mechanism and the PCI bus for providing an interface between the PCI bus and the routing mechanism; a plurality of write buffers coupled to the bridge, wherein a plurality of write transactions on the PCI bus are combined into one cache line sized transfer to the routing mechanism; a plurality of read buffers coupled to the bridge, wherein data fetched according to a read request from the device is stored in the read buffers and the device can access the read buffer multiple times to retrieve the data; a prefetcher coupled to the bridge, wherein when the PCI device generates a read request and there is no corresponding data contained in the read buffers, the bridge reads sequential cache lines until the read buffers are full, a page boundary is encountered, or the read buffers are caused to be flushed.
Claim 3
Dependent Claim
28 words
The computer system of claim 1, wherein the read buffers are flushed when a non-sequential read is issued, the device issues a write, or the buffers are invalidated.
Claim 4
Dependent Claim
19 words
The computer system of claim 1, wherein there are different types of read operations including a precise read operation.
Claim 5
Dependent Claim
35 words
The computer system of claim 1 further comprising an interrupt controller coupled to the PCI bus, wherein the interrupt controller performs buffer management for devices coupled to the PCI bus by using an interrupt signal.
Claim 6
Dependent Claim
36 words
The computer system of claim 1 further comprising a mechanism for performing write gathering, wherein a plurality of write transactions on the PCI bus are combined into one cache line sized transfer to the routing mechanism.
Claim 7
Dependent Claim
18 words
The computer system of claim 3, wherein the different types of read operations include a non-precise read operation.
Claim 8
Dependent Claim
18 words
The computer system of claim 6, wherein the different types of read operations include a pre-fetch read operation.
Claim 9
Dependent Claim
134 words
A computer system comprising: a routing mechanism for routing packets of data; a processor coupled to the routing mechanism for processing the data; a memory coupled to the routing mechanism for storing the data; a PCI bus for conveying PCI format data; a PCI device coupled to the PCI bus; a bridge coupled between the routing mechanism and the PCI bus for providing an interface between the PCI bus and the routing mechanism; a plurality of write buffers coupled to the bridge, wherein a plurality of write transactions on the PCI bus are combined into one cache line sized transfer to the routing mechanism; a controller coupled to the PCI bus for controlling multiple streams of data and multiple virtual buffers so that a bit is used to select or clear particular virtual buffers.
Claim 10
Dependent Claim
134 words
A computer system comprising: a routing mechanism for routing packets of data; a processor coupled to the routing mechanism for processing the data; a memory coupled to the routing mechanism for storing the data; a PCI bus for conveying PCI format data; a PCI device coupled to the PCI bus; a bridge coupled between the routing mechanism and the PCI bus for providing an interface between the PCI bus and the routing mechanism; a plurality of write buffers coupled to the bridge, wherein a plurality of write transactions on the PCI bus are combined into one cache line sized transfer to the routing mechanism; a controller coupled to the PCI bus for controlling multiple streams of data and multiple virtual buffers so that a bit is used to select or clear particular virtual buffers.
Claim 11
Dependent Claim
144 words
In a computer system, a method for minimizing memory latencies corresponding to memory accesses through a bridge coupled between a memory and a device, comprising the steps of: issuing a write request by the device; transmitting the write request over a PCI bus to the bridge; combining a plurality of write requests; storing the write requests into a write buffer; transmitting a single write transaction corresponding to the combination of write requests from the bridge to the memory through a routing mechanism; pre-fetching data from the memory according to a read request generated by the device; storing the data in a plurality of read buffers coupled to the bridge; accessing the read buffer multiple times to retrieve the data; continuing to prefetch data until either the read buffers are full, a page boundary is encountered, or the read buffers are caused to be flushed.
Claim 12
Dependent Claim
144 words
In a computer system, a method for minimizing memory latencies corresponding to memory accesses through a bridge coupled between a memory and a device, comprising the steps of: issuing a write request by the device; transmitting the write request over a PCI bus to the bridge; combining a plurality of write requests; storing the write requests into a write buffer; transmitting a single write transaction corresponding to the combination of write requests from the bridge to the memory through a routing mechanism; pre-fetching data from the memory according to a read request generated by the device; storing the data in a plurality of read buffers coupled to the bridge; accessing the read buffer multiple times to retrieve the data; continuing to prefetch data until either the read buffers are full, a page boundary is encountered, or the read buffers are caused to be flushed.
Claim 13
Dependent Claim
31 words
The method of claim 9 further comprising the step of flushing the read buffers flushed when a non-sequential read is issued, the device issues a write, or the buffers are invalidated.
Claim 14
Dependent Claim
18 words
The method of claim 9, wherein there are different types of read operations including a precise read operation.
Claim 15
Dependent Claim
25 words
The method of claim 9 further comprising the step of performing buffer management for devices coupled to the PCI bus by using an interrupt signal.
Claim 16
Dependent Claim
35 words
The computer system of claim 9 further comprising the step of write gathering, wherein a plurality of write transactions on the PCI bus are combined into one cache line sized transfer to the routing mechanism.
Claim 17
Dependent Claim
17 words
The method of claim 11, wherein the different types of read operations include a non-precise read operation.
Claim 18
Dependent Claim
17 words
The method of claim 14, wherein the different types of read operations include a pre-fetch read operation.
Claim 19
Dependent Claim
103 words
In a computer system, a method for minimizing memory latencies corresponding to memory accesses through a bridge coupled between a memory and a device, comprising the steps of: issuing a write request by the device; transmitting the write request over a PCI bus to the bridge; combining a plurality of write requests; storing the write requests into a write buffer; transmitting a single write transaction corresponding to the combination of write requests from the bridge to the memory through a routing mechanism; controlling multiple streams of data and multiple virtual buffers, wherein a bit is used to select or clear particular virtual buffers.
Claim 20
Dependent Claim
103 words
In a computer system, a method for minimizing memory latencies corresponding to memory accesses through a bridge coupled between a memory and a device, comprising the steps of: issuing a write request by the device; transmitting the write request over a PCI bus to the bridge; combining a plurality of write requests; storing the write requests into a write buffer; transmitting a single write transaction corresponding to the combination of write requests from the bridge to the memory through a routing mechanism; controlling multiple streams of data and multiple virtual buffers, wherein a bit is used to select or clear particular virtual buffers.
References Cited (Backward Citations)
US5664117A
Cited
US5761450A
Cited
US5594882A
Cited
US5771359A
Cited
US5673399A
Cited
US5761461A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |