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US5951664A
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Computer system having a multimedia bus and including improved time slotting and bus allocation
Assignee: Advanced Micro Devices Inc
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Filing: 1997-09-10
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Granted: 1999-09-14
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Expires: 2017-09-10
Abstract
Abstract A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The multimedia bus is preferably time sliced wherein time slices or time slots are allocated in proportion to the required bandwidth. Each multimedia device includes programmable time slotting logic which determines the appropriate time slot. In one embodiment, the time slices are each a constant size and a number of the equal sized time slots are allocated to respective data streams in proportion to the required bandwidth. Alternatively, the time slots are dynamically sized or allocated to data streams in proportion to the required bandwidth. The computer system of the present invention thus provides greater performance for real-time applications than prior systems.
Inventors
- 👤 Andy Lambrecht
- 👤 Rodney Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:53
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/238; G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F13/36; G06F13/368; G06F13/372; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4013; G06F13/4022; G06F13/4027
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
181 words
A computer system including a bus with improved time slotting features, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes bus interface logic; a bus coupled to the bridge logic, wherein said bus includes a plurality of data lines for transmitting data; a plurality of devices coupled to said bus, wherein each of said devices perform operations on said bus, wherein each of said devices includes bus interface logic for accessing said bus and performing data transfers on said bus; wherein each of said plurality of devices includes intelligent time slotting logic which controls access to the bus, wherein the intelligent time slotting logic for each respective device operates to selectively assign a respective time slot for bus access to said respective device, wherein each of the plurality of devices has guaranteed access to the bus during the respective time slot without requiring arbitration for the bus.
Claim 2
Dependent Claim
181 words
A computer system including a bus with improved time slotting features, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes bus interface logic; a bus coupled to the bridge logic, wherein said bus includes a plurality of data lines for transmitting data; a plurality of devices coupled to said bus, wherein each of said devices perform operations on said bus, wherein each of said devices includes bus interface logic for accessing said bus and performing data transfers on said bus; wherein each of said plurality of devices includes intelligent time slotting logic which controls access to the bus, wherein the intelligent time slotting logic for each respective device operates to selectively assign a respective time slot for bus access to said respective device, wherein each of the plurality of devices has guaranteed access to the bus during the respective time slot without requiring arbitration for the bus.
Claim 3
Dependent Claim
33 words
The computer system of claim 1, wherein said intelligent time slotting logic for each respective device comprises one or more timers and counters for determining said respective time slot for said respective device.
Claim 4
Dependent Claim
27 words
The computer system of claim 2, wherein said intelligent time slotting logic for each respective device comprises a programmable time slot memory for storing time slot information.
Claim 5
Dependent Claim
25 words
The computer system of claim 3, wherein said time slot information comprises a respective time slot position and a time slot length on the bus.
Claim 6
Dependent Claim
19 words
The computer system of claim 4, wherein said time slot length is the same for each of said devices.
Claim 7
Dependent Claim
23 words
The computer system of claim 4, wherein said time slot length is dynamically allocated for each of said devices based on required bandwidth.
Claim 8
Dependent Claim
23 words
The computer system of claim 3, wherein said programmable time slot memory is adapted to receive said time slot information from said CPU.
Claim 9
Dependent Claim
26 words
The computer system of claim 7, wherein said CPU programs said programmable time slot memory with said time slot information at start-up of the computer system.
Claim 10
Dependent Claim
33 words
The computer system of claim 7, wherein said CPU dynamically programs said programmable time slot memory with said time slot information dependent on real time processes and applications executing in the computer system.
Claim 11
Dependent Claim
33 words
The computer system of claim 1, wherein said intelligent time slotting logic for each respective device comprises bus monitoring logic for monitoring conditions on the bus and for detecting collisions on the bus.
Claim 12
Dependent Claim
31 words
The computer system of claim 10, wherein said bus monitoring logic ensures that the bus has been inactive for a preset period of time before allowing a data transfer to begin.
Claim 13
Dependent Claim
13 words
The computer system of claim 1, wherein said bus is an expansion bus.
Claim 14
Dependent Claim
33 words
The computer system of claim 1, further comprising: an expansion bus for transmitting data coupled to the bridge logic; wherein said bus is a multimedia bus, and wherein said devices are multimedia devices.
Claim 15
Independent Claim
151 words
A method for allocating use of a time-sliced bus connecting a plurality of devices without arbitration, each of said devices having an intelligent bus interface module, wherein said method comprises: the intelligent bus interface modules in each of said devices monitoring traffic on the time-sliced bus; each of said devices determining if the traffic on the time-sliced bus is directed to an address mapped to the respective device; and each of the intelligent bus interface modules counting time-slices to determine transmission ownership of the time-slices, wherein each of the devices receives transmission ownership information from its respective intelligent bus interface module and is configured to transmit a data stream on the time-sliced bus only during the time-slices for which the device has ownership, wherein each of said devices has guaranteed access to the time-sliced bus during the time-slices for which the device has ownership without requiring arbitration for the time-sliced bus.
Claim 16
Independent Claim
151 words
A method for allocating use of a time-sliced bus connecting a plurality of devices without arbitration, each of said devices having an intelligent bus interface module, wherein said method comprises: the intelligent bus interface modules in each of said devices monitoring traffic on the time-sliced bus; each of said devices determining if the traffic on the time-sliced bus is directed to an address mapped to the respective device; and each of the intelligent bus interface modules counting time-slices to determine transmission ownership of the time-slices, wherein each of the devices receives transmission ownership information from its respective intelligent bus interface module and is configured to transmit a data stream on the time-sliced bus only during the time-slices for which the device has ownership, wherein each of said devices has guaranteed access to the time-sliced bus during the time-slices for which the device has ownership without requiring arbitration for the time-sliced bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |