US5956618A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for producing multi-level metallization in an integrated circuit
Assignee: Nokia of America Corp
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Filing: 1997-03-27
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Granted: 1999-09-21
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Expires: 2017-03-27
Abstract
Abstract A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.
Inventors
- 👤 Chun-Ting Liu
- 👤 Kuo-Hua Lee
- 👤 Ruichen Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/071; Y; Y10; Y10S; Y10S438/00; Y10S438/942
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A method of fabricating a multilayered integrated circuit in which a plurality of patterns of conducting material are selectively formed on at least one dielectric layer of said integrated circuit comprising the steps of: creating a mask by forming a first opaque pattern over a transparent base wherein said first opaque pattern being a grid selectively removing portions of opaque regions forming a plurality of transparent regions of said transparent base corresponding to said plurality of patterns of conducting material; forming a second opaque pattern on said mask corresponding to the pattern of said conducting material in the region from which said first opaque pattern material is removed; depositing, in a single deposition, a space filling material as an unused feature on said at least one dielectric layer corresponding to said opaque pattern of said mask, and said conducting material on said first at least one dielectric layer corresponding to said second opaque pattern in said plurality of transparent regions of said mask.
Claim 2
Independent Claim
163 words
A method of fabricating a multilayered integrated circuit in which a plurality of patterns of conducting material are selectively formed on at least one dielectric layer of said integrated circuit comprising the steps of: creating a mask by forming a first opaque pattern over a transparent base wherein said first opaque pattern being a grid selectively removing portions of opaque regions forming a plurality of transparent regions of said transparent base corresponding to said plurality of patterns of conducting material; forming a second opaque pattern on said mask corresponding to the pattern of said conducting material in the region from which said first opaque pattern material is removed; depositing, in a single deposition, a space filling material as an unused feature on said at least one dielectric layer corresponding to said opaque pattern of said mask, and said conducting material on said first at least one dielectric layer corresponding to said second opaque pattern in said plurality of transparent regions of said mask.
Claim 3
Dependent Claim
28 words
The method of claim 1, in which said unused feature formed by said space filling material is of substantially the same height and spacing as said conducting material.
Claim 4
Dependent Claim
31 words
The method of claim 1, further comprising the step of depositing at least another dielectric layer of substantially uniform height over said previously deposited conducting material and said space filling material.
Claim 5
Dependent Claim
28 words
The method of claim 3, in which said unused feature formed by said space filling material is of substantially the same height and spacing as said conducting material.
Claim 6
Dependent Claim
53 words
The method according to claim 1, wherein said step of depositing, in a single deposition, comprises photolithographically patterning a photoresist and etching away an exposed metal layer on said dielectric layer except at opaque portions of said mask to thereby define said conducting features and said space filling material on said dielectric layer.
Claim 7
Dependent Claim
18 words
The method according to claim 1, wherein each of said conductive features comprises a line of conductive material.
Claim 8
Dependent Claim
21 words
The method according to claim 1, wherein said space filling material is of substantially the same height as said conductive features.
Claim 9
Independent Claim
201 words
A method of fabricating a multilayered integrated circuit in which a plurality of conductive features are selectively formed on at least one dielectric layer of said integrated circuit, said method comprising the steps of: creating a mask by forming, during a computer-aided design (CAD) stage, a first pattern associated with space filling material to be formed on said at least one dielectric layer, wherein said first pattern being a grid and modifying said grid pattern in the CAD stage by removing portions of said first pattern to form a plurality of regions devoid of said first pattern, and then superimposing, during the CAD stage, a second pattern on said first pattern such that said second pattern is within said regions from which said grid pattern is removed, wherein said mask is formed with first and second opaque patterns over a transparent base corresponding to said first and second patterns, respectively, formed in the CAD stage; and employing said mask to form, on said at least one dielectric layer in a single operation, a space filling material as an unused feature corresponding to said first opaque pattern, and said plurality of conductive features corresponding to said second opaque pattern of said mask.
Claim 10
Independent Claim
201 words
A method of fabricating a multilayered integrated circuit in which a plurality of conductive features are selectively formed on at least one dielectric layer of said integrated circuit, said method comprising the steps of: creating a mask by forming, during a computer-aided design (CAD) stage, a first pattern associated with space filling material to be formed on said at least one dielectric layer, wherein said first pattern being a grid and modifying said grid pattern in the CAD stage by removing portions of said first pattern to form a plurality of regions devoid of said first pattern, and then superimposing, during the CAD stage, a second pattern on said first pattern such that said second pattern is within said regions from which said grid pattern is removed, wherein said mask is formed with first and second opaque patterns over a transparent base corresponding to said first and second patterns, respectively, formed in the CAD stage; and employing said mask to form, on said at least one dielectric layer in a single operation, a space filling material as an unused feature corresponding to said first opaque pattern, and said plurality of conductive features corresponding to said second opaque pattern of said mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-20 | 2011-03-22 | 2011-09-21 | $7700.00 | Window Closed / Lapsed |