Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells each to be accessed in accordance with selected row and column are arranged in a matrix; an external terminal used to monitor the current in each of said plurality of memory cells; a single bus line, connected to said external terminal, for conducting said current to said external terminal; a transfer gate group, provided between said bus line and said memory cell array and stacked so as to form a tree structure having multiple stages of transfer gates, for selectively connecting said bus line to any column in said memory cell array; and a decoder circuit for controlling to select the transfer gates for each of the multiple stages in said transfer gate group.

Claim 3

A semiconductor memory device according to claim 1, wherein said memory cells include regular memory cells to be accessed for data acquisition and a dummy cell for generating a reference potential to read the data from said regular memory cells, and redundancy memory cells replaceable with said regular memory cells.

Claim 4

A semiconductor memory device according to claim 2, further comprising a switch circuit, provided between said transfer gate group and said bus line, for electrically connecting either said regular memory cells' side or said dummy cell's side to said bus line via said transfer gate group.

Claim 5

A semiconductor memory device according to claim 1, wherein an output of said decoder circuit is obtained from a potential boosted inside the decoder circuit.

Claim 6

A semiconductor memory device according to claim 1, wherein during the monitoring of the current in each of said memory cells, a monitoring power-supply voltage is supplied to a row decoder for selecting said row.

Claim 7

A semiconductor memory device according to claim 5, wherein said monitoring power-supply voltage is variable.

Claim 8

A semiconductor memory device according to claim 6, wherein a threshold voltage for each of said memory cells is determined from the current monitored at said external terminal.

Claim 9

A semiconductor memory device according to claim 6, wherein said monitoring power-supply voltage is supplied from an external terminal different from said external terminal.

Claim 10

A semiconductor memory device according to claim 1, further comprising a plurality of terminals for transmitting signals corresponding to the columns in said memory cell array, wherein said decoder circuit controls to select said transfer gates in accordance with a combination of the signals supplied from said plurality of terminals.

Claim 11

A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells each to be accessed in accordance with selected row and column are arranged in a matrix; an external terminal used to monitor the current in each of said plurality of memory cells; a single bus line, connected to said external terminal, for conducting said current to said external terminal; a transfer gate group, provided between said bus line and said memory cell array and stacked so as to form a tree structure having multiple stages of transfer gates, for selectively connecting said bus line to any column in said memory cell array; a decoder circuit for controlling to select the transfer gates for each of the multiple stages in said transfer gate group; and a plurality of terminals for transmitting signals corresponding to the columns in said memory cell array, wherein one of said plurality of terminals also serves as said external terminal.

Claim 12

A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells each to be accessed in accordance with selected row and column are arranged in a matrix; an external terminal used to monitor the current in each of said plurality of memory cells; a single bus line, connected to said external terminal, for conducting said current to said external terminal; a transfer gate group, provided between said bus line and said memory cell array and stacked so as to form a tree structure having multiple stages of transfer gates, for selectively connecting said bus line to any column in said memory cell array; a decoder circuit for controlling to select the transfer gates for each of the multiple stages in said transfer gate group; and a plurality of terminals for transmitting signals corresponding to the columns in said memory cell array, wherein one of said plurality of terminals also serves as said external terminal.

Claim 13

A semiconductor memory device according to claim 10, wherein said external terminal is a terminal other than a terminal for intput/output.

Claim 14

A semiconductor memory device comprising: a memory cell array that always allows the memory cells to be accessed in parallel; decode means capable of selecting a signal corresponding to any one of the memory cells during said parallel accessing; and a single bus line for transmitting said signal selected by said decode means to the outside of the device.

Claim 15

A semiconductor memory device comprising: a memory cell array that always allows the memory cells to be accessed in parallel; decode means capable of selecting a signal corresponding to any one of the memory cells during said parallel accessing; and a single bus line for transmitting said signal selected by said decode means to the outside of the device.

Claim 16

A semiconductor memory device according to claim 12, wherein said decode means selects the signal in accordance with a combination of externally supplied signals.

Claim 17

A semiconductor memory device according to claim 12, wherein said decode means is activated when a test signal is externally supplied and applies to said memory cell array a signal potential different from that during the ordinary parallel access to the memory cells.

Claim 18

A semiconductor memory device according to claim 12, further comprising an external terminal connected to said bus line and used to monitor a current corresponding to the memory cell selected by said decode means.

Claim 19

A semiconductor memory device according to claim 15, wherein a threshold voltage for said memory cell is determined from the current monitored at said external terminal.

Claim 20

A semiconductor memory device according to claim 15, wherein said decode means includes: a transfer gate group, provided between said bus line and said memory cell array and stacked so as to form a tree structure having multiple stages of transfer gates, and a decoder circuit for controlling to select the transfer gates for each of the multiple stages in said transfer gate group.

Claim 21

A semiconductor memory device according to claim 17, wherein said decoder circuit has a level shifter and controls to select the transfer gates using the high-potential signal outputted from said level shifter.

Claim 22

A semiconductor memory device according to claim 17, wherein a control gate of a memory cell selected by said decode means is applied with two or more kinds of voltages via said bus line.