Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Claim 1

A wafer having at least one integrated circuit, the wafer being formed in accordance with a method comprising the steps of: forming a first active layer having a multiplicity of active conductive traces on a surface of a substrate of the wafer, the active conductive traces each being arranged to electrically couple associated elements of an associated integrated circuit on the wafer, there being gaps between adjacent ones of the active conductive traces; determining a uniform pattern density for the surface of the wafer; forming a multiplicity of dummy raised lines on the surface of the substrate in the gaps, wherein the dummy raised lines are not arranged to electrically couple any elements in the integrated circuit, the multiplicity of dummy raised lines and the multiplicity of active conductive traces having said uniform pattern density over the surface of the substrate; depositing an insulating layer over the active conductive traces to electrically insulate the active conductive traces; polishing the surface of the insulating layer to provide a planar surface on the wafer, whereby the dummy raised lines cooperate with the active conductive traces to improve standardized polishing of the wafer; and forming a plurality of additional active layers over said first active layer by repeating the foregoing steps for forming said first active layer, each of the additional active layers having substantially said uniform pattern density of said first active layer.