US5999451A — Byte-wide write scheme for a page flash device

Claim 1

Independent Claim 96 words

In an array of floating gate memory cells including sets of floating gate cells and a buffer which can be coupled with a set of floating gate cells among the sets, a method of loading data into a selected portion of the set of floating gate cells, the method comprising: storing contents of the set of floating gate cells into the buffer; storing the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells; and storing contents of the buffer into the set of floating gate cells.

Claim 2

Dependent Claim 96 words

In an array of floating gate memory cells including sets of floating gate cells and a buffer which can be coupled with a set of floating gate cells among the sets, a method of loading data into a selected portion of the set of floating gate cells, the method comprising: storing contents of the set of floating gate cells into the buffer; storing the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells; and storing contents of the buffer into the set of floating gate cells.

Claim 3

Dependent Claim 13 words

The method of claim 1, wherein the set comprises a row of cells.

Claim 4

Dependent Claim 11 words

The method of claim 1, wherein the data comprises a byte.

Claim 5

Dependent Claim 19 words

The method of claim 1, wherein the data comprises at least 4 bits and not more than 128 bits.

Claim 6

Dependent Claim 13 words

The method of claim 1, wherein the set comprises at least 500 bits.

Claim 7

Dependent Claim 13 words

The method of claim 3, wherein the set comprises at least 500 bits.

Claim 8

Dependent Claim 13 words

The method of claim 4, wherein the set comprises at least 500 bits.

Claim 9

Dependent Claim 14 words

The method of claim 1, wherein the buffer comprises static random access memory (SRAM).

Claim 10

Dependent Claim 30 words

The method of claim 1, wherein the buffer comprises bit latches coupled to respective bit lines and the set of floating gate cells comprises a row of floating gate cells.

Claim 11

Dependent Claim 91 words

The method of claim 9, wherein storing the contents of the row into the buffer comprises: setting a set of bit lines to a pre-charge voltage level; applying a word line voltage to a word line of the row; and responding to changes in voltage levels of the bit lines in response to the word line voltage, to store a constant in the bit latches coupled to the bit lines on which the voltage levels of the bit lines passes a threshold during the step of applying the word line voltage.

Claim 12

Dependent Claim 57 words

The method of claim 9, wherein storing contents of the buffer into the row comprises: erasing the row; applying a word line voltage to a word line of the row; and applying a programming potential to a set of bit lines in response to one binary value in the bit latches, but not the other binary value.

Claim 13

Dependent Claim 24 words

The method of claim 11, wherein storing contents of the buffer into the row further comprises: verifying that the row has been successfully programmed.

Claim 14

Dependent Claim 51 words

The method of claim 1, comprising: before the storing the data into the portion of the buffer, storing the data into a register coupled to the buffer; and wherein storing the data into a portion of the buffer comprises causing the data in the register to be stored into the buffer.

Claim 15

Dependent Claim 111 words

In an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled with respective bit lines, a method of loading data into a selected portion of row in the array, the method comprising: storing contents of the row of floating gate cells into the bit latches; storing the data into a set of the bit latches corresponding to the selected portion of the row in the array of floating gate cells; and storing contents of the bit latches into the row in the array of floating gate cells.

Claim 16

Dependent Claim 111 words

In an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled with respective bit lines, a method of loading data into a selected portion of row in the array, the method comprising: storing contents of the row of floating gate cells into the bit latches; storing the data into a set of the bit latches corresponding to the selected portion of the row in the array of floating gate cells; and storing contents of the bit latches into the row in the array of floating gate cells.

Claim 17

Dependent Claim 26 words

The method of claim 14, wherein the row of floating gate cells comprises at least 500 cells and the data comprises not more than 256 bits.

Claim 18

Dependent Claim 61 words

The method of claim 15, comprising: before the storing the data into the set of bit latches, storing the data into a register coupled to the bit latches; and wherein the storing the data into a portion of the buffer comprises causing the data in the register to be stored into bit latches corresponding to the selected portion of the row.

Claim 19

Dependent Claim 67 words

The method of claim 16, wherein causing the data in the register to be stored into bit latches corresponding to the selected portion of the row comprises: coupling a multiplexer between the register and the bit latches; and applying to the multiplexer a portion of an address of the selected location in the array, the portion of the address corresponding to the selected portion of the row.

Claim 20

Dependent Claim 30 words

The method of claim 16, wherein storing contents of the row into the bit latches comprises: resetting a bit line address; and setting a word line corresponding to the row.

Claim 21

Dependent Claim 32 words

The method of claim 18, wherein storing contents of the bit latches into the row comprises: erasing the row; and programming cells in the row based on contents of the bit latches.

Claim 22

Dependent Claim 34 words

The method of claim 19, wherein programming the row based on contents of the bit latches comprises applying a programming potential to the bit lines in response to the contents of the bit latches.

Claim 23

Dependent Claim 14 words

The method of claim 20, wherein the programming potential comprises greater than 5 volts.

Claim 24

Dependent Claim 42 words

The method of claim 20, wherein applying a programming potential comprises providing pass transistors, having gate terminals, between a supply of the programming potential and the bit lines, and connecting outputs of respective bit latches to gate terminals of the pass transistors.

Claim 25

Dependent Claim 50 words

The method of claim 20, wherein applying a programming potential includes first applying the programming potential to bit lines in a first set of bit lines among the bit lines, and then applying the programming potential to bit lines in a second set of bit lines among the bit lines.

Claim 26

Dependent Claim 36 words

The method of claim 23, bit lines in the first set of bit lines comprising every other bit line and bit lines in the second set of set of bit lines comprising the remaining bit lines.

Claim 27

Dependent Claim 60 words

The method of claim 20, wherein storing contents of the bit latches into the row further comprises: verifying that the row has been programmed according to the contents of the bit latches; and if the row has not been programmed according to the contents of the bit latches, then reprogramming the row based on the contents of the bit latches.

Claim 28

Dependent Claim 104 words

In an array of floating gate memory cells including a buffer which can be coupled with respective sets of bytes of the array, a method of loading a byte into the array at a particular address, the method comprising: storing the byte into a register; storing a set of bytes from a portion of the array into the buffer, the portion of the array corresponding to a part of the address; storing the byte from the register into a location of the buffer, the location corresponding to another part of the address; and storing contents of the buffer into the portion of the array.

Claim 29

Dependent Claim 104 words

In an array of floating gate memory cells including a buffer which can be coupled with respective sets of bytes of the array, a method of loading a byte into the array at a particular address, the method comprising: storing the byte into a register; storing a set of bytes from a portion of the array into the buffer, the portion of the array corresponding to a part of the address; storing the byte from the register into a location of the buffer, the location corresponding to another part of the address; and storing contents of the buffer into the portion of the array.

Claim 30

Dependent Claim 16 words

The method of claim 26, wherein the portion of the array comprises a row of cells.

Claim 31

Dependent Claim 54 words

The method of claim 26, wherein the array includes word lines coupled to respective rows of cells, the set of bytes comprises a row of cells, and storing the set of bytes from a portion of the array comprises applying a word line voltage to a word line corresponding to the row of cells.

Claim 32

Dependent Claim 39 words

The method of claim 26, wherein storing the byte from the register into a location of the buffer comprises: coupling a multiplexer between the register and the buffer; and applying to the multiplexer the another part of the address.

Claim 33

Dependent Claim 40 words

The method of claim 26, wherein storing contents of the buffer into the portion of the array comprises: erasing the portion of the array; programming bits in the portion of the array based on the contents of the bit latches.

Claim 34

Dependent Claim 40 words

The method of claim 26, wherein programming the portion of the array based on the contents of the bit latches comprises: in response to the contents of the buffer, applying a programming potential to bit lines coupled to the buffer.

Claim 35

Dependent Claim 14 words

The method of claim 31, wherein the programming potential comprises greater than 5 volts.

Claim 36

Dependent Claim 42 words

The method of claim 31, wherein applying a programming potential comprises providing pass transistors, having gate terminals, between a supply of the programming potential and the bit lines, and connecting respective outputs of the buffer to gate terminals of the pass transistors.

Claim 37

Dependent Claim 50 words

The method of claim 31, wherein applying a programming potential includes first applying the programming potential to bit lines in a first set of bit lines among the bit lines, and then applying the programming potential to bit lines in a second set of bit lines among the bit lines.

Claim 38

Dependent Claim 36 words

The method of claim 34, bit lines in the first set of bit lines comprising every other bit line and bit lines in the second set of set of bit lines comprising the remaining bit lines.

Claim 39

Dependent Claim 63 words

The method of claim 27, wherein storing contents of the buffer into the portion of the array comprises: verifying that cells in the portion have been programmed according to the contents of the buffer; and if the cells in the portion have not been programmed according to the contents of the buffer, then reprogramming the portion based on the contents of the buffer.

Claim 40

Dependent Claim 143 words

An integrated circuit comprising: an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array; and bit latches coupled with respective bit lines, respective rows including pluralities of bytes; a register including at least a byte of storage and less storage than the bit latches; a multiplexer coupled to the register and the bit latches; and circuitry to control the word lines, the bit latches, and the multiplexer to store data into the register, to select a row of the array, to store the selected row from the array into the bit latches, to store the data from the register into selected bit latches from among the bit latches, and to store contents of the bit latches into the selected row of the array.

Claim 41

Dependent Claim 143 words

An integrated circuit comprising: an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array; and bit latches coupled with respective bit lines, respective rows including pluralities of bytes; a register including at least a byte of storage and less storage than the bit latches; a multiplexer coupled to the register and the bit latches; and circuitry to control the word lines, the bit latches, and the multiplexer to store data into the register, to select a row of the array, to store the selected row from the array into the bit latches, to store the data from the register into selected bit latches from among the bit latches, and to store contents of the bit latches into the selected row of the array.

Claim 42

Dependent Claim 38 words

The integrated circuit of claim 37, comprising: circuitry to erase cells in the selected row of the array; and circuitry to program particular cells in the selected row of the array based on contents of the bit latches.

Claim 43

Dependent Claim 45 words

The integrated circuit of claim 38, the circuitry to program particular cells in the selected row of the array comprises: circuitry to, in response to the contents of the bit latches, apply a programming potential to bit lines among the bit lines in the array.

Claim 44

Dependent Claim 15 words

The integrated circuit of claim 39, wherein the programming potential comprises greater than 5 volts.

Claim 45

Dependent Claim 40 words

The integrated circuit of claim 39, comprising pass transistors, having gate terminals, between a supply of the programming potential and the bit lines, and circuitry to connect respective outputs of the bit latches to gate terminals of the pass transistors.

Claim 46

Dependent Claim 42 words

The integrated circuit of claim 39, comprising circuitry to first apply the programming potential to a first set of bit lines among the bit lines, and then apply the programming potential to a second set of bit lines among the bit lines.

Claim 47

Dependent Claim 37 words

The integrated circuit of claim 42, bit lines in the first set of bit lines comprising every other bit line and bit lines in the second set of set of bit lines comprising the remaining bit lines.

Claim 48

Dependent Claim 52 words

The integrated circuit of claim 37, comprising circuitry to verify that the row has been programmed according to the contents of the bit latches; and if the row has not been programmed according to the contents of the bit latches, then reprogram the row based on the contents of the bit latches.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-12-06	2003-06-07	2003-12-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-12-06	2007-06-07	2007-12-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-12-06	2011-06-07	2011-12-07	$7700.00	Window Closed / Lapsed

Byte-wide write scheme for a page flash device

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag