US6006296A — Scalable memory controller

Claim 1

Independent Claim 131 words

A system for selectively interconnecting inputs to outputs on different sections of a single ASIC chip having different functionality modes, to achieve scaling of performance and number of requesters, comprising within a single ASIC chip type: a memory input section having a plurality of inputs and a plurality of outputs; a memory controller section having a plurality of inputs and a plurality of outputs; a memory output section having a plurality of inputs and a plurality of outputs; first bypassing means for bypassing said memory input section; second bypassing means for bypassing said memory controller section; and third bypassing means for selectively bypassing said memory output section, whereby, normally connected inputs to outputs are selectively bypassed; whereby a plurality of different controller modes of operation are obtainable from the same chip.

Claim 2

Independent Claim 131 words

A system for selectively interconnecting inputs to outputs on different sections of a single ASIC chip having different functionality modes, to achieve scaling of performance and number of requesters, comprising within a single ASIC chip type: a memory input section having a plurality of inputs and a plurality of outputs; a memory controller section having a plurality of inputs and a plurality of outputs; a memory output section having a plurality of inputs and a plurality of outputs; first bypassing means for bypassing said memory input section; second bypassing means for bypassing said memory controller section; and third bypassing means for selectively bypassing said memory output section, whereby, normally connected inputs to outputs are selectively bypassed; whereby a plurality of different controller modes of operation are obtainable from the same chip.

Claim 3

Dependent Claim 39 words

The system as recited in claim 1, wherein said first bypassing means comprises selective coupling means for selectively coupling said memory input section inputs directly to ones of said memory controller section inputs and said memory output section inputs.

Claim 4

Dependent Claim 34 words

The system as recited in claim 1, wherein said second bypassing means comprises selective coupling means for selectively coupling said memory controller section outputs to ones of said memory output section inputs and outputs.

Claim 5

Dependent Claim 62 words

The system as recited in claim 1, wherein said third bypassing means comprises: first selective coupling means for selectively coupling said memory input section outputs directly to ones of said memory controller section inputs and said memory output section outputs; and second selective coupling means for selectively coupling said memory controller section outputs directly to ones of said memory output section outputs.

Claim 6

Dependent Claim 85 words

The system as recited in claim 1, further comprising means, having: first selective coupling means for selectively coupling said memory input section inputs through said memory input section to said memory input section outputs; second selective coupling means for selectively coupling said memory input section outputs through said memory controller to the output of the memory controller; and third selective coupling means for selectively coupling the output of the memory controller section through said memory output section to the outputs of the memory output section.

Claim 7

Dependent Claim 20 words

The system as recited in claim 1, wherein the memory input section comprises an input queue to queue memory requests.

Claim 8

Dependent Claim 27 words

The system as recited in claim 6, where said input queue comprises a plurality of queues, one for each of said memory input section inputs and outputs.

Claim 9

Dependent Claim 48 words

The system as recited in claim 1, where in said memory controller section comprises: an input selection device; and means for selectively coupling an input to said input selection device to processing logic, said processing logic performing required memory accesses and output results of said required memory accesses.

Claim 10

Dependent Claim 23 words

The system as recited in claim 1, wherein the memory output section comprises an output queue to queue any results of memory requests.

Claim 11

Dependent Claim 27 words

The system as recited in claim 9, where said output queue comprises a plurality of queues, one for each of said memory output section inputs and outputs.

Claim 12

Dependent Claim 18 words

The system as recited in claim 5, wherein said first, second, and third selective coupling means comprise multiplexers.

Claim 13

Dependent Claim 21 words

The system as recited in claim 5, further comprising configuration means for configuring said first, second, and third selective coupling means.

Claim 14

Dependent Claim 29 words

The system as recited in claim 12, wherein said configuration means comprises initialization means to initialize said first, second, and third selective coupling means according to a predetermined mode.

Claim 15

Dependent Claim 117 words

A memory controller system comprising: one or more input ASICs, moded to input a plurality of inputs and having a plurality of outputs; one or more memory controller ASICs, moded to control a memory subsection having a plurality of outputs; one or more output ASICs moded to output a plurality of outputs and having a plurality of inputs; means for selectively coupling said outputs of said input ASICs to said inputs of said memory controller ASICs; means for selectively coupling said outputs of said memory controller ASIC to said inputs of said output ASICs; and wherein said input ASICs, said memory controller ASICs, and output ASICs have the same architectural design, but are configured in different modalities.

Claim 16

Dependent Claim 117 words

A memory controller system comprising: one or more input ASICs, moded to input a plurality of inputs and having a plurality of outputs; one or more memory controller ASICs, moded to control a memory subsection having a plurality of outputs; one or more output ASICs moded to output a plurality of outputs and having a plurality of inputs; means for selectively coupling said outputs of said input ASICs to said inputs of said memory controller ASICs; means for selectively coupling said outputs of said memory controller ASIC to said inputs of said output ASICs; and wherein said input ASICs, said memory controller ASICs, and output ASICs have the same architectural design, but are configured in different modalities.

Claim 17

Dependent Claim 18 words

The memory system of claim 14, comprising different numbers of input ASICs, memory controller ASICs, and output ASICs.

Claim 18

Dependent Claim 168 words

A memory controller system comprising: a plurality of ASICs arranged in parallel and scalable to increase the number of requests handled simultaneously, each said ASIC having thereon a memory input section having a plurality of inputs adapted to receive memory requests from plural requestors, each said ASIC having thereon a memory output section having a plurality of outputs adapted to access addresses in a main memory for writing into and reading from the main memory in response to requests from said requester, each said ASIC having thereon a memory controller section having a plurality of inputs normally coupled between said memory input section and said memory output section, and bypass circuit means coupled to the inputs and the outputs between said sections, and selection means active to configure said memory controller system for memory input or memory output or memory controller functionality or as a memory controller system having all three functions and the number of simultaneous requests are scalable by configuring sections in series and in parallel.

Claim 19

Dependent Claim 168 words

A memory controller system comprising: a plurality of ASICs arranged in parallel and scalable to increase the number of requests handled simultaneously, each said ASIC having thereon a memory input section having a plurality of inputs adapted to receive memory requests from plural requestors, each said ASIC having thereon a memory output section having a plurality of outputs adapted to access addresses in a main memory for writing into and reading from the main memory in response to requests from said requester, each said ASIC having thereon a memory controller section having a plurality of inputs normally coupled between said memory input section and said memory output section, and bypass circuit means coupled to the inputs and the outputs between said sections, and selection means active to configure said memory controller system for memory input or memory output or memory controller functionality or as a memory controller system having all three functions and the number of simultaneous requests are scalable by configuring sections in series and in parallel.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-12-20	2003-06-21	2003-12-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-12-20	2007-06-21	2007-12-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-12-20	2011-06-21	2011-12-21	$7700.00	Window Closed / Lapsed

Scalable memory controller

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