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US6011293A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having a structure for detecting a boosted potential

Assignee: Renesas Electronics Corp
•
Filing: 1998-04-23
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Granted: 2000-01-04
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Expires: 2018-04-23
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Abstract

Abstract A p-type well and an n-type well surrounding the p-type well are formed in a p-type semiconductor substrate under a field insulating film. A polysilicon resistance film is formed on the field insulating film simultaneously with a floating gate formed in a memory cell region. A polycide conductive film is formed on a interlayer insulating film simultaneously with an auxiliary bit line formed in the memory cell region, and the polycide conductive film is connected to the resistance film by a contact formed in a via hole. A wiring line formed on an interlayer insulating film is connected to the polycide conductive film by a contact formed in a via hole penetrating the interlayer insulating film. The two via holes are formed at positions corresponding to regions in the p-type well. A negative voltage is applied to the wiring line, and the potential of a predetermined point on the resistance film is measured.

Inventors

  • 👤 Kojiro Yuzuriha
  • 👤 Makoto Ooi
  • 👤 Shinichi Kobayashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 10:26
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/47; H10B20/00

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 216 words
A semiconductor device comprising: a p-type semiconductor substrate; a p-type well formed in a surface of said p-type semiconductor substrate; an n-type well covering the bottom surface and the side surface of said p-type well; a surface insulating film formed on the surface of said semiconductor substrate including said p-type well and said n-type well; a resistance film formed on said surface insulating film so that at least a portion thereof lies over said p-type well; a first insulating film formed on said surface insulating film so as to cover said resistance film; a conductive film formed on said first insulating film so that at least a portion thereof lies over said resistance film; a second insulating film formed on said first insulating film so as to cover said conductive film; a wiring line formed on said second insulating film so that at least a portion thereof lies over said conductive film; a first contact penetrating said first insulating film to connect one end of said resistance film to said conductive film; and a second contact penetrating said second insulating film to connect said conductive film to said wiring line; wherein said p-type well extends outward by a predetermined length from the extension lines toward the p-type well of said first and the second contacts respectively.
Claim 2
Dependent Claim 216 words
A semiconductor device comprising: a p-type semiconductor substrate; a p-type well formed in a surface of said p-type semiconductor substrate; an n-type well covering the bottom surface and the side surface of said p-type well; a surface insulating film formed on the surface of said semiconductor substrate including said p-type well and said n-type well; a resistance film formed on said surface insulating film so that at least a portion thereof lies over said p-type well; a first insulating film formed on said surface insulating film so as to cover said resistance film; a conductive film formed on said first insulating film so that at least a portion thereof lies over said resistance film; a second insulating film formed on said first insulating film so as to cover said conductive film; a wiring line formed on said second insulating film so that at least a portion thereof lies over said conductive film; a first contact penetrating said first insulating film to connect one end of said resistance film to said conductive film; and a second contact penetrating said second insulating film to connect said conductive film to said wiring line; wherein said p-type well extends outward by a predetermined length from the extension lines toward the p-type well of said first and the second contacts respectively.
Claim 3
Dependent Claim 78 words
A semiconductor device according to claim 1, further comprising a memory cell region, said memory cell region including a plurality of memory cells each comprised of a floating gate transistor, said memory cell region further including auxiliary bit lines of a divided bit line structure, wherein said resistance film is formed simultaneously with said floating gates of said memory cell region, and said conductive film is formed simultaneously with said auxiliary bit lines of said memory cell region.
Claim 4
Dependent Claim 40 words
The semiconductor device according to claim 2, wherein said resistance film is a polysilicon layer, said conductive film is a two-layer film consisting of a polysilicon layer and a tungsten silicide layer, and said wiring line is an aluminum layer.
Claim 5
Dependent Claim 64 words
The semiconductor device according to claim 3, wherein a potential of said resistance film at a predetermined position between the opposite ends of said resistance film is measured while a generated negative voltage is applied to said wiring line which is electrically connected to one end of said resistance film, and another generated voltage is applied to the other end of said resistance film.
Claim 6
Dependent Claim 37 words
The semiconductor device according to claim 4, wherein said p-type well is set at a floating potential, said n-type well is set at a supply potential, and said p-type semiconductor substrate is set at a ground potential.
Claim 7
Dependent Claim 64 words
The semiconductor device according to claim 2, wherein a potential of said resistance film at a predetermined position between the opposite ends of said resistance film is measured while a generated negative voltage is applied to said wiring line which is electrically connected to one end of said resistance film, and another generated voltage is applied to the other end of said resistance film.
Claim 8
Dependent Claim 37 words
The semiconductor device according to claim 6, wherein said p-type well is set at a floating potential, said n-type well is set at a supply potential, and said p-type semiconductor substrate is set at a ground potential.
Claim 9
Dependent Claim 40 words
The semiconductor device according to claim 1, wherein said resistance film is a polysilicon layer, said conductive film is a two-layer film consisting of a polysilicon layer and a tungsten silicide layer, and said wiring line is an aluminum layer.
Claim 10
Dependent Claim 64 words
The semiconductor device according to claim 8, wherein a potential of said resistance film at a predetermined position between the opposite ends of said resistance film is measured while a generated negative voltage is applied to said wiring line which is electrically connected to one end of said resistance film, and another generated voltage is applied to the other end of said resistance film.
Claim 11
Dependent Claim 37 words
The semiconductor device according to claim 9, wherein said p-type well is set at a floating potential, said n-type well is set at a supply potential, and said p-type semiconductor substrate is set at a ground potential.
Claim 12
Dependent Claim 64 words
The semiconductor device according to claim 1, wherein a potential of said resistance film at a predetermined position between the opposite ends of said resistance film is measured while a generated negative voltage is applied to said wiring line which is electrically connected to one end of said resistance film, and another generated voltage is applied to the other end of said resistance film.
Claim 13
Dependent Claim 37 words
The semiconductor device according to claim 11, wherein said p-type well is set at a floating potential, said n-type well is set at a supply potential, and said p-type semiconductor substrate is set at a ground potential.

References Cited (Backward Citations)

JPH0383361A Cited
US5751050A Cited
US5801418A Cited
US5874770A Cited
US5903033A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-01-03 2003-07-05 2004-01-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-01-03 2007-07-05 2008-01-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-01-03 2011-07-05 2012-01-04 $7700.00 Window Closed / Lapsed

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