Manufacturing method and apparatus of a semiconductor integrated circuit device

Claim 1

An apparatus for manufacturing a semiconductor integrated circuit device comprising: a data input means for generating a general wiring net data for connection of a plurality of input and output terminals of a plurality of logic cells and for generating delay time data relating to signals from the output terminals to the input terminals, said general wiring net data comprising a first wiring net data for connecting the plurality of output terminals to at least one of the input terminals and a second wiring net data for connecting a single output terminal to the plurality of input terminals, said first wiring net data being combined with said delay time data for generating a first simulation design model, said first wiring net data being used for generating a second simulation design model, and said second wiring net data being used for generating a third simulation design model; a first determining means for distinguishing which one of said first and second wiring net data is input from said data input means; a selecting means for selecting one of said simulation design models in accordance with a determination of said first determining means; a first model generating means for generating said first simulation design model based on said first wiring net data and said delay time data when said selecting means selects said first simulation design model; a second model generating means for generating said second simulation design model based on said first wiring net data when said selecting means selects said second simulation design model; and a third model generating means for generating said third simulation model based on said second wiring net data when said first determining means determines that said wiring net data is said second wiring net data.

Claim 2

An apparatus for manufacturing a semiconductor integrated circuit device comprising: a data input means for generating a general wiring net data for connection of a plurality of input and output terminals of a plurality of logic cells and for generating delay time data relating to signals from the output terminals to the input terminals, said general wiring net data comprising a first wiring net data for connecting the plurality of output terminals to at least one of the input terminals and a second wiring net data for connecting a single output terminal to the plurality of input terminals, said first wiring net data being combined with said delay time data for generating a first simulation design model, said first wiring net data being used for generating a second simulation design model, and said second wiring net data being used for generating a third simulation design model; a first determining means for distinguishing which one of said first and second wiring net data is input from said data input means; a selecting means for selecting one of said simulation design models in accordance with a determination of said first determining means; a first model generating means for generating said first simulation design model based on said first wiring net data and said delay time data when said selecting means selects said first simulation design model; a second model generating means for generating said second simulation design model based on said first wiring net data when said selecting means selects said second simulation design model; and a third model generating means for generating said third simulation model based on said second wiring net data when said first determining means determines that said wiring net data is said second wiring net data.

Claim 6

A method for disposing a plurality of logic cells included in a semiconductor integrated circuit device on a semiconductor chip based on a net wiring list including a plurality of wiring nets for connecting output terminals and input terminals of said logic cells to each other, the method comprising the steps of: setting a wiring length between any pair of said terminals among said input and output terminals within a specific wiring net to a predetermined wiring length; providing a bypass route having a specified length between said pair of terminals when the actual wiring length between said pair of terminals is less than said predetermined wiring length, the length of said bypass route corresponding to said predetermined wiring length; disposing a dummy cell in said bypass route, said dummy cell having intermediate terminals connected with said pair of terminals; and disposing the plurality of logic cells including said dummy cell, onto said semiconductor chip in accordance with said predetermined wiring length.

Claim 7

A method for disposing a plurality of logic cells included in a semiconductor integrated circuit device on a semiconductor chip based on a net wiring list including a plurality of wiring nets for connecting output terminals and input terminals of said logic cells to each other, the method comprising the steps of: setting a wiring length between any pair of said terminals among said input and output terminals within a specific wiring net to a predetermined wiring length; providing a bypass route having a specified length between said pair of terminals when the actual wiring length between said pair of terminals is less than said predetermined wiring length, the length of said bypass route corresponding to said predetermined wiring length; disposing a dummy cell in said bypass route, said dummy cell having intermediate terminals connected with said pair of terminals; and disposing the plurality of logic cells including said dummy cell, onto said semiconductor chip in accordance with said predetermined wiring length.