Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable; a select gate connected to a select gate line for connecting a memory cell unit to a bitline; a first precharge circuit connected to a first node of the bitline, for supplying a power supply voltage higher than 0 V; a second precharge circuit connected to a second node of the bitline, for supplying a precharge voltage higher than the power supply voltage in programming of data; and a latch circuit for holding data transferred to the bitline.

Claim 3

A semiconductor memory device according to claim 1, wherein the precharge voltage is generated by a booster circuit provided in the semiconductor memory device.

Claim 4

A semiconductor memory device according to claim 1, wherein the precharge voltage is supplied from outside of the semiconductor memory device.

Claim 5

A semiconductor memory device according to claim 1, wherein said second precharge circuit comprises an n-channel MOS transistor in which the source is connected to the bitline and the drain is connected to a precharge voltage source.

Claim 6

A semiconductor memory device comprising: a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable; a select gate connected to a select gate line for connecting a memory cell unit to a bitline; a row selecting circuit for selecting a word line of the memory cell array and the select gate line; a voltage generating circuit connected to the row selecting circuit and for generating a programming voltage; a column selecting circuit for selecting the bitline of the memory cell array; a precharge circuit connected to a first node of the bitline for supplying a precharge voltage higher than a power supply voltage in programming of data; and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell; a control circuit for controlling the voltage generating circuit, the precharge circuit and the transfer gate, wherein the control circuit executes in programming data into the memory cell: a first operation in which a signal is supplied to the precharge circuit, and a voltage of a channel of a memory cell in a selected memory cell unit is charged to the precharge voltage via the bitline; a second operation in which a voltage of the channel of a memory cell is biased to a programming prohibiting voltage higher than the precharge voltage by supplying the programming voltage to a word line through which programming is performed in a selected memory cell from the voltage generating circuit and by capacitive coupling between the word line and the channel of the memory cell connected thereto; and a third operation, in which the transfer gate is made conductive, and in which potentials of a bitline and the channel voltage of the memory cell unit are controlled based on programming data held in the latch circuit.

Claim 7

A semiconductor memory device comprising: a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable; a select gate connected to a select gate line for connecting a memory cell unit to a bitline; a row selecting circuit for selecting a word line of the memory cell array and the select gate line; a voltage generating circuit connected to the row selecting circuit and for generating a programming voltage; a column selecting circuit for selecting the bitline of the memory cell array; a precharge circuit connected to a first node of the bitline for supplying a precharge voltage higher than a power supply voltage in programming of data; and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell; a control circuit for controlling the voltage generating circuit, the precharge circuit and the transfer gate, wherein the control circuit executes in programming data into the memory cell: a first operation in which a signal is supplied to the precharge circuit, and a voltage of a channel of a memory cell in a selected memory cell unit is charged to the precharge voltage via the bitline; a second operation in which a voltage of the channel of a memory cell is biased to a programming prohibiting voltage higher than the precharge voltage by supplying the programming voltage to a word line through which programming is performed in a selected memory cell from the voltage generating circuit and by capacitive coupling between the word line and the channel of the memory cell connected thereto; and a third operation, in which the transfer gate is made conductive, and in which potentials of a bitline and the channel voltage of the memory cell unit are controlled based on programming data held in the latch circuit.

Claim 8

A semiconductor memory device according to claim 5, wherein the precharge circuit comprises an n-channel MOS transistor in which the source is connected to the bitline and the drain is connected to a precharge voltage source.

Claim 9

A semiconductor memory device according to claim 6, wherein the voltage generating circuit supplies a voltage higher than the precharge voltage to the gate of the MOS transistor constituting the precharge circuit, all the word lines of the selected memory cell unit and the select gate line in programming.

Claim 10

A semiconductor memory device according to claim 5, wherein the control circuit electrically disconnects the precharge circuit from the bitline in the second operation.

Claim 11

A semiconductor memory device according to claim 5, wherein the control circuit reduces potential of a word line in which the programming voltage is supplied to the adjacent word line to a voltage equal to or lower than the power supply voltage in the second operation.

Claim 12

A semiconductor memory device according to claim 5, wherein the control circuit reduces potentials of a word line in which the programming voltage is supplied to the adjacent word line and the select gate line connected to the select gate to a voltage equal to or lower than the power supply voltage in the second operation.

Claim 13

A semiconductor memory device according to claim 10, wherein the control circuit electrically disconnects the precharge circuit from the bitline in the third operation.

Claim 14

A semiconductor memory device according to claim 5, further comprising a load transistor connected between the second node of the bitline and a electric source for suppressing reduction in potential of the bitline, wherein the control circuit executes an operation in which the load transistor is made conductive and reduction in potential of the bitline through which programming is prohibited is suppressed in control of potentials of the bitline and the channel of the memory cell based on programming data held in the latch circuit in the third operation.

Claim 15

A semiconductor memory device according to claim 5, wherein the control circuit executes the third operation after executing the second operation.

Claim 16

A semiconductor memory device according to claim 5, wherein the control circuit executes the second operation after executing the third operation.

Claim 17

A semiconductor memory device comprising: a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable; a select gate connected to a select gate line for connecting a memory cell unit to a bitline; a row selecting circuit for selecting a word line of the memory cell array and the select gate line; a voltage generating circuit connected to the row selecting circuit for generating a first voltage higher than a power supply voltage by at least a threshold voltage of the select gate and a programming voltage; a column selecting circuit for selecting the bitline of the memory cell array, wherein in programming data into a memory cell, a power supply voltage is supplied to a non-programming bitline, the first voltage is supplied to the select gate line from the voltage generating circuit, channels of the memory cells in the memory cell unit, to which the non-programming bitline is connected, are charged to a precharge voltage higher than a differential voltage between a potential of the non-programming bitline and a threshold voltage of the select gate and brought into a floating state, thereafter the programming voltage produced by the voltage generating circuit is supplied to the word line in a selected memory cell unit, the channels of the memory cells in the floating state are biased to a programming prohibiting potential higher than the precharge voltage by capacitive coupling with the word line.

Claim 18

A semiconductor memory device comprising: a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable; a select gate connected to a select gate line for connecting a memory cell unit to a bitline; a row selecting circuit for selecting a word line of the memory cell array and the select gate line; a voltage generating circuit connected to the row selecting circuit for generating a first voltage higher than a power supply voltage by at least a threshold voltage of the select gate and a programming voltage; a column selecting circuit for selecting the bitline of the memory cell array, wherein in programming data into a memory cell, a power supply voltage is supplied to a non-programming bitline, the first voltage is supplied to the select gate line from the voltage generating circuit, channels of the memory cells in the memory cell unit, to which the non-programming bitline is connected, are charged to a precharge voltage higher than a differential voltage between a potential of the non-programming bitline and a threshold voltage of the select gate and brought into a floating state, thereafter the programming voltage produced by the voltage generating circuit is supplied to the word line in a selected memory cell unit, the channels of the memory cells in the floating state are biased to a programming prohibiting potential higher than the precharge voltage by capacitive coupling with the word line.

Claim 19

A semiconductor memory device according to claim 15, wherein the potential supplied to the non-programming bit line is a power supply voltage in a chip or a power supply voltage from outside of the chip.

Claim 20

A semiconductor memory device according to claim 15, wherein the voltage generating circuit generates the first voltage higher than a power supply voltage by the threshold voltage of the select gate or the memory cell, and the first voltage is supplied to the select gate line or the word line from the voltage generating circuit in programming of data to the memory cell.

Claim 21

A semiconductor memory device according to claim 15, wherein, in programming of data to the memory cell, after the channels of the memory cells are charged to the precharge voltage higher than the differential voltage between the potential of the non-programming bitline and the threshold voltage of the select gate, a voltage supplied to the select gate line is reduced to make the select gate cut off.

Claim 22

A semiconductor memory device according to claim 15, wherein, in programming of data to the memory cell, after the channels of the memory cells are charged to the precharge voltage higher than the differential voltage between potential of the non-programming bitline and the threshold voltage of the select gate, a voltage supplied to the select gate line is reduced to a second voltage equal to or lower than the power supply voltage and equal to or higher than a threshold voltage of the select gate from the first voltage and the select gate is cut off.

Claim 23

A semiconductor memory device according to claim 19, wherein a timing at which the voltage supplied to the select gate line is reduced to the second voltage from the first voltage; a timing at which the programming voltage is supplied to a selected word line; and a timing at which potential of a non-selected word line of a selected memory cell unit is increased to about half the programming voltage are almost the same.

Claim 24

The semiconductor memory device according to claim 1, wherein channels of the plurality of the memory cells constituting a selected memory cell unit are charged to the precharge voltage.

Claim 25

The semiconductor memory device according to claim 21, wherein at least one of two memory cells adjacent to a memory cell to be programmed is cut off before a voltage of a word line of the memory cell to be programmed is raised to the programming voltage.

Claim 26

The semiconductor memory device according to claim 22, wherein said select gate is cut off before the voltage of the word line of the memory cell to be programmed is raised to the programming voltage.

Claim 27

The semiconductor memory device according to claim 23, wherein said second precharge circuit supplies the precharge voltage until data is transferred from said latch circuit to the memory cell to be programmed.

Claim 28

The semiconductor memory device according to claim 23, wherein a bitline not to be programmed is charged while a bitline to be programmed performs a programming operation.

Claim 29

The semiconductor memory device according to claim 23, wherein said latch circuit is conductive to said bitline before a programming voltage is supplied to the word line of the memory cell to be programmed.