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US6058046A
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Nonvolatile semiconductor memory cell capable of saving overwritten cell and its saving method
Assignee: Toshiba Corp
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Filing: 1999-07-21
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Granted: 2000-05-02
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Expires: 2019-07-21
Abstract
Abstract If data is read from a selected memory cell at the time of overwrite verifying, a Potential of a bit line is changed in accordance with data. If a transistor is turned on, a latch circuit is set in accordance with data of the bit line. In a case where there is a memory cell being in an overwrite state, data of the selected memory cell is latched to the latch circuit, and data corresponding to one page is erased. Thereafter, a normally writing operation is executed by data latch to the latch circuit, thereby the memory cell being in the overwrite state can be used as a normal threshold voltage.
Inventors
- 👤 Keniti Imamiya
- 👤 Hiroshi Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:05
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3413; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
335 words
A nonvolatile semiconductor memory device comprising: a plurality of memory cells, each having a control gate; a plurality of word lines, each being connected to the control gate of the plurality of said memory cells; a latch circuit having a first node and a second node; a bit line on which data is transferred from/to the memory cells; a first transistor having a first gate electrode and a first terminal, the first terminal being connected to the first node of the latch circuit, and a first timing signal being applied to the first gate electrode; a second transistor having a first terminal and a second gate electrode, the first terminal of the second transistor being connected to the second node of the latch circuit, and a second timing signal being applied to the second gate electrode; a third transistor having a first terminal and a third gate electrode, the first terminal of the third transistor being connected to a second terminal of the second transistor, a second terminal of the third transistor being connected to a ground node, and the third gate electrode being connected to the bit line; a fourth transistor having first and second terminals and a fourth gate electrode, the first and second terminals of the fourth transistor being connected between the first node of the latch circuit and the bit line, and a third timing signal being applied to the fourth gate electrode; a fifth transistor having a first terminal and a fifth gate electrode, the first terminal of the fifth transistor being connected to a second terminal of the first transistor, a second terminal of the fifth transistor being connected to the ground node, and the fifth gate electrode being connected to the bit line; and a pair of data lines having a first data line and a second data line, said first data line being connected to the first node of the latch circuit and said second data line being connected to the second node of the latch circuit.
Claim 2
Dependent Claim
335 words
A nonvolatile semiconductor memory device comprising: a plurality of memory cells, each having a control gate; a plurality of word lines, each being connected to the control gate of the plurality of said memory cells; a latch circuit having a first node and a second node; a bit line on which data is transferred from/to the memory cells; a first transistor having a first gate electrode and a first terminal, the first terminal being connected to the first node of the latch circuit, and a first timing signal being applied to the first gate electrode; a second transistor having a first terminal and a second gate electrode, the first terminal of the second transistor being connected to the second node of the latch circuit, and a second timing signal being applied to the second gate electrode; a third transistor having a first terminal and a third gate electrode, the first terminal of the third transistor being connected to a second terminal of the second transistor, a second terminal of the third transistor being connected to a ground node, and the third gate electrode being connected to the bit line; a fourth transistor having first and second terminals and a fourth gate electrode, the first and second terminals of the fourth transistor being connected between the first node of the latch circuit and the bit line, and a third timing signal being applied to the fourth gate electrode; a fifth transistor having a first terminal and a fifth gate electrode, the first terminal of the fifth transistor being connected to a second terminal of the first transistor, a second terminal of the fifth transistor being connected to the ground node, and the fifth gate electrode being connected to the bit line; and a pair of data lines having a first data line and a second data line, said first data line being connected to the first node of the latch circuit and said second data line being connected to the second node of the latch circuit.
Claim 3
Dependent Claim
291 words
A nonvolatile semiconductor memory device comprising: a plurality of memory cells, each having a control gate; a plurality of word lines, each being connected to the control gate of the plurality of said memory cells; a latch circuit having a first node and a second node; a bit line on which data is transferred from/to the memory cells; a first transistor having a first terminal and a first gate electrode, the first terminal being connected to the second node of the latch circuit, a second terminal being connected to the bit line, and a first timing signal being applied to the first gate electrode; a second transistor having a first terminal and a second gate electrode, the first terminal of the second transistor being connected to the second node of the latch circuit, and a second timing signal being applied to the second gate electrode; a third transistor having a first terminal and a third gate electrode, the first terminal of the third transistor being connected to a second terminal of the second transistor, a second terminal of the third transistor being connected to a ground node, and the third gate electrode being connected to the bit line; a fourth transistor having first and second terminals and a fourth gate electrode, the first and second terminals of the fourth transistor being connected between the first node of the latch circuit and the bit line, and a third timing signal being applied to the fourth gate electrode; and a pair of data lines having a first data line and a second data line, said first data line being connected to the first node of the latch circuit and said second data line being connected to the second node of the latch circuit.
Claim 4
Dependent Claim
291 words
A nonvolatile semiconductor memory device comprising: a plurality of memory cells, each having a control gate; a plurality of word lines, each being connected to the control gate of the plurality of said memory cells; a latch circuit having a first node and a second node; a bit line on which data is transferred from/to the memory cells; a first transistor having a first terminal and a first gate electrode, the first terminal being connected to the second node of the latch circuit, a second terminal being connected to the bit line, and a first timing signal being applied to the first gate electrode; a second transistor having a first terminal and a second gate electrode, the first terminal of the second transistor being connected to the second node of the latch circuit, and a second timing signal being applied to the second gate electrode; a third transistor having a first terminal and a third gate electrode, the first terminal of the third transistor being connected to a second terminal of the second transistor, a second terminal of the third transistor being connected to a ground node, and the third gate electrode being connected to the bit line; a fourth transistor having first and second terminals and a fourth gate electrode, the first and second terminals of the fourth transistor being connected between the first node of the latch circuit and the bit line, and a third timing signal being applied to the fourth gate electrode; and a pair of data lines having a first data line and a second data line, said first data line being connected to the first node of the latch circuit and said second data line being connected to the second node of the latch circuit.
References Cited (Backward Citations)
US5691941A
Cited
US5959895A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-02 | 2003-11-01 | 2004-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-02 | 2007-11-01 | 2008-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-02 | 2011-11-01 | 2012-05-02 | $7700.00 | Window Closed / Lapsed |