US6058472A
Expired / Lapsed
US
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Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine
Assignee: Oracle America Inc
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Filing: 1997-06-25
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Granted: 2000-05-02
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Expires: 2017-06-25
Abstract
Abstract A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been retired. Each entry has several fields amongst which are the data and the addresses of the memory operations. An incoming load checks its address against the addresses of all the stores. If there is a match against an older store, then the load must have received old data from the data cache and the load operation is replayed to seek data from the memory disambiguation buffer on the replay. If on the other hand, there were no matches on any older store, the load is assumed to have received the right data from the data cache (assuming a data cache hit). An incoming store checks its address against the addresses of all younger loads. If there is a match against any younger load, then the younger load is replayed along with all of its dependents.
Inventors
- 👤 Ramesh Panwar
- 👤 P.K. Chidambaran
- 👤 Ricky C. Hetherington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 23:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3834; G06F9/3861
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
121 words
A processor for executing out-of-order instructions comprising: an instruction scheduling window for determining an execution order of said instructions; and a memory disambiguation buffer, coupled to said instruction scheduling window, for enqueueing addresses and data of unretired load and store instructions, said memory disambiguation buffer operative to effectuate a replay of an incoming load instruction if a match is determined between an address of said incoming load instruction and an address of enqueued older store instruction, said replay utilizing data regarding a youngest matched store instruction queued in said memory disambiguation buffer; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 2
Dependent Claim
121 words
A processor for executing out-of-order instructions comprising: an instruction scheduling window for determining an execution order of said instructions; and a memory disambiguation buffer, coupled to said instruction scheduling window, for enqueueing addresses and data of unretired load and store instructions, said memory disambiguation buffer operative to effectuate a replay of an incoming load instruction if a match is determined between an address of said incoming load instruction and an address of enqueued older store instruction, said replay utilizing data regarding a youngest matched store instruction queued in said memory disambiguation buffer; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 3
Dependent Claim
37 words
The processor of claim 1 wherein said memory disambiguation buffer is further operative to retire said incoming load instruction if a match is not found between said incoming load instruction address and an enqueued older store instruction.
Claim 4
Dependent Claim
15 words
The processor of claim 1 wherein said instruction scheduling window comprises an m entry buffer.
Claim 5
Dependent Claim
17 words
The processor of claim 3 wherein said memory disambiguation buffer comprises an n entry buffer wherein n<m.
Claim 6
Dependent Claim
10 words
The processor of claim 4, wherein n is substantially m/2.
Claim 7
Dependent Claim
127 words
A processor for executing out-of-order instructions comprising: an instruction scheduling window for determining an execution order of said instructions; a memory disambiguation buffer coupled to said instruction scheduling window for enqueuing addresses and data of unretired load and store instructions, said memory disambiguation buffer operative to effectuate a replay through the instruction scheduling window of an oldest one of said younger load instructions if a match is determined between said incoming store instruction address and an enqueued younger load instruction address, said replay utilizing data stored in said buffer regarding the oldest one of said younger load instructions; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 8
Dependent Claim
127 words
A processor for executing out-of-order instructions comprising: an instruction scheduling window for determining an execution order of said instructions; a memory disambiguation buffer coupled to said instruction scheduling window for enqueuing addresses and data of unretired load and store instructions, said memory disambiguation buffer operative to effectuate a replay through the instruction scheduling window of an oldest one of said younger load instructions if a match is determined between said incoming store instruction address and an enqueued younger load instruction address, said replay utilizing data stored in said buffer regarding the oldest one of said younger load instructions; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 9
Dependent Claim
38 words
The processor of claim 6 wherein said memory disambiguation buffer is further operative to enqueue said incoming store instruction if a match is not found between said incoming store instruction address and an enqueued younger load instruction address.
Claim 10
Dependent Claim
15 words
The processor of claim 6 wherein said instruction scheduling window comprises an m entry buffer.
Claim 11
Dependent Claim
17 words
The processor of claim 8 wherein said memory disambiguation buffer comprises an n entry buffer wherein n<m.
Claim 12
Dependent Claim
10 words
The processor of claim 9, wherein n is substantially m/2.
Claim 13
Dependent Claim
109 words
A memory disambiguation buffer for an out-of-order processor comprising: means for enqueuing addresses and data of unretired load and store instructions in a buffer; means for checking an address of an incoming load instruction against said enqueued addresses of store instructions; means for replaying said incoming load instruction if a match is determined between said incoming load instruction address and an enqueued older store instruction address, said replay utilizing data regarding a youngest matched store instruction stored in said buffer; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 14
Dependent Claim
109 words
A memory disambiguation buffer for an out-of-order processor comprising: means for enqueuing addresses and data of unretired load and store instructions in a buffer; means for checking an address of an incoming load instruction against said enqueued addresses of store instructions; means for replaying said incoming load instruction if a match is determined between said incoming load instruction address and an enqueued older store instruction address, said replay utilizing data regarding a youngest matched store instruction stored in said buffer; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 15
Dependent Claim
17 words
The memory disambiguation buffer of claim 11 wherein said means for enqueuing comprises an n entry buffer.
Claim 16
Dependent Claim
28 words
The memory disambiguation buffer of claim 11 wherein said means for enqueuing comprises: means for entering said unretired load and store instructions in said buffer in program order.
Claim 17
Dependent Claim
35 words
The memory disambiguation buffer of claim 11 further comprising: means for retiring disambiguated load and store instructions; and means for removing said addresses and data of said disambiguated load and store instructions from said buffer.
Claim 18
Dependent Claim
34 words
The memory disambiguation buffer of claim 11 further comprising: means for retiring said incoming load instruction if a match is not found between said incoming load instruction address and an enqueued older store instruction.
Claim 19
Dependent Claim
118 words
A memory disambiguation buffer for an out-of-order processor comprising: means for enqueueing addresses and data of unretired load and store instructions in a buffer; means for checking an address of an incoming store instruction against said enqueued addresses of younger load instructions; means for replaying an oldest one of said younger load instructions if a match is determined between said incoming store instruction address and an enqueued younger load instruction address, said replay utilizing identification data stored in said buffer regarding the oldest one of said younger load instructions; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 20
Dependent Claim
118 words
A memory disambiguation buffer for an out-of-order processor comprising: means for enqueueing addresses and data of unretired load and store instructions in a buffer; means for checking an address of an incoming store instruction against said enqueued addresses of younger load instructions; means for replaying an oldest one of said younger load instructions if a match is determined between said incoming store instruction address and an enqueued younger load instruction address, said replay utilizing identification data stored in said buffer regarding the oldest one of said younger load instructions; wherein said load instruction is partially speculatively executed before said replay; and wherein said replay involves re-execution of at least some machine actions required to execute said load instruction.
Claim 21
Dependent Claim
16 words
The memory disambiguation buffer of claim 16 wherein said enqueuing means comprises an n entry buffer.
Claim 22
Dependent Claim
27 words
The memory disambiguation buffer of claim 16 wherein said enqueuing means comprises: means for entering said unretired load and store instructions in said buffer in program order.
Claim 23
Dependent Claim
35 words
The memory disambiguation buffer of claim 16 further comprising: means for retiring disambiguated load and store instructions; and means for removing said addresses and data of said disambiguated load and store instructions from said buffer.
Claim 24
Dependent Claim
35 words
The memory disambiguation buffer of claim 16 further comprising: means for enqueuing said incoming store instruction if a match is not found between said incoming store instruction address and an enqueued younger load instruction address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-02 | 2003-11-01 | 2004-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-02 | 2007-11-01 | 2008-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-02 | 2011-11-01 | 2012-05-02 | $7700.00 | Window Closed / Lapsed |