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Method for the manufacture of a power semiconductor component

Assignee: Infineon Technologies AG
•
Filing: 1999-02-01
•
Granted: 2000-05-23
•
Expires: 2019-02-01
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Abstract

Abstract Component structures of, for example, IGBTs are manufactured on the respective top sides of two substrates, the substrates are thinned proceeding from their respective back sides, and, after polishing, the back sides of the thinned substrates are durably electrically conductively connected to one another by wafer bonding.

Inventors

  • 👤 Daniel Reznik
  • 👤 Hans-Joachim Schulze
  • 👤 Wolfgang Eckhard

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 22:19
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10W; H10W99/00; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/038; H10D18/01; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 137 words
A method for manufacturing a power semiconductor component, comprises the steps of: providing a first substrate composed of an electrically conductively doped semiconductor material having a top side and bottom side opposite each other, and a second substrate composed of said electrically conductive doped semiconductor material having a top side and a bottom side opposite each other; generating doped regions and contacts on said top side of said first substrate and on said top side of said second substrate; thinning said first substrate from said back side of said first substrate to produce a thinned first substrate and thinning said second substrate from said back side of said second substrate to produce a thinned second substrate; and mechanically and electrically conductively joining said thinned first substrate and said thinned second substrate at the respective back sides thereof.
Claim 2
Independent Claim 137 words
A method for manufacturing a power semiconductor component, comprises the steps of: providing a first substrate composed of an electrically conductively doped semiconductor material having a top side and bottom side opposite each other, and a second substrate composed of said electrically conductive doped semiconductor material having a top side and a bottom side opposite each other; generating doped regions and contacts on said top side of said first substrate and on said top side of said second substrate; thinning said first substrate from said back side of said first substrate to produce a thinned first substrate and thinning said second substrate from said back side of said second substrate to produce a thinned second substrate; and mechanically and electrically conductively joining said thinned first substrate and said thinned second substrate at the respective back sides thereof.
Claim 3
Dependent Claim 33 words
A method as claimed in claim 1 wherein the step of joining said thinned first substrate and said thinned second substrate comprises wafer bonding said thinned first substrate and said thinned second substrate.
Claim 4
Dependent Claim 31 words
A method as claimed in claim 2 wherein the step of wafer bonding comprises wafer bonding said thinned first substrate and said thinned second substrate at a temperature below 350° C.
Claim 5
Dependent Claim 54 words
A method as claimed in claim 1 wherein the step of generating doped regions and contacts on said top side of said first substrate and on said top side of said second substrate comprises generating IGBT structures on said top side of said first substrate and on said top side of said second substrate.
Claim 6
Dependent Claim 54 words
A method as claimed in claim 1 wherein the step of generating doped regions and contacts on said top side of said first substrate and on said top side of said second substrate comprises generating GTO thyristors on said top side of said first substrate and on said top side of said second substrate.

References Cited (Backward Citations)

US5141889A Cited
US5183769A Cited
US5489787A Cited
US5591991A Cited
US5608237A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-05-23 2003-11-22 2004-05-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-05-23 2007-11-22 2008-05-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-05-23 2011-11-22 2012-05-23 $7700.00 Window Closed / Lapsed

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