Frequency comparison and generation in an integrated processor

Claim 2

An integrated processor configured to receive a reference clock signal and an external clock signal and comprising: a processor core; a peripheral bus interface coupled to said processor core; and a clock circuit coupled to said processor core, wherein said processor core, peripheral bus interface, and clock circuit are formed on a single monolithic substrate; wherein said clock circuit is configured to compare a frequency of said reference clock signal to a frequency of said external clock signal and to output an internal clock signal, wherein said clock circuit is configured to generate said internal clock signal with a frequency equal to said frequency of said reference clock signal in response to detecting a first frequency relationship between said reference clock signal and said external clock signal, and wherein said clock circuit is configured to generate said internal clock signal with a frequency which is a multiple of said frequency of said reference clock signal in response to detecting a second frequency relationship between said reference clock signal and said external clock signal, wherein said multiple is not equal to one; wherein said clock circuit comprises a comparator circuit that compares said frequency of said reference clock signal to said frequency of said external clock signal and outputs a control signal indicative of whether said frequency of said reference clock signal equals said frequency of said external clock signal; and a phase-locked loop configured to receive said control signal of said comparator circuit and said reference clock signal and configured to output said internal clock signal.

Claim 3

The integrated processor of claim 1 wherein said multiple of said frequency of said reference clock signal is twice said frequency of said reference clock signal.

Claim 4

The integrated processor of claim 2 wherein said frequency of said internal clock signal is twice said frequency of said reference clock signal in response to said comparison detecting said frequency of said reference clock signal equals said frequency of said external clock signal.

Claim 5

The integrated processor of claim 2 wherein said frequency of said internal clock signal is equal to said frequency of said reference clock signal in response to said comparison detecting said frequency of said reference clock signal is twice said frequency of said external clock signal.

Claim 6

The integrated processor of claim 1 wherein said clock circuit is coupled to said peripheral bus interface and said internal clock signal provides a timing signal to said peripheral bus interface.

Claim 7

The integrated processor of claim 1 wherein said phase-locked loop comprises: a phase comparator configured to receive said reference clock signal and a feedback signal, and configured to output an error signal indicative of a phase relationship between said reference clock signal and said feedback signal; a low-pass filter configured to receive said error signal of said phase comparator; a voltage controlled oscillator configured to receive an output of said low-pass filter and output an oscillator signal; a clock divider circuit configured to receive said oscillator signal and said control signal and output said internal clock signal, wherein a number by which said frequency of said clock signal is divided is determined by said control signal; and a feedback circuit coupled to receive said internal clock signal and output said feedback signal.

Claim 8

The integrated processor of claim 1 wherein said peripheral bus interface interfaces said processor core to a peripheral component interface (PCI) bus.

Claim 9

The integrated processor of claim 1 wherein said clock circuit further outputs a processor clock to said processor core.

Claim 10

A clock circuit comprising: a clock generator configured to output an external clock signal and a reference clock signal; a phase detector circuit coupled to said external clock signal, an internal clock signal and said reference clock signal and configured to output a control signal and a phase enable signal, wherein said control signal is indicative of a frequency relationship between said external clock signal and said reference clock signal, and wherein said phase enable signal is indicative of a phase relationship between said external clock signal and said internal clock signal; a clock multiplier circuit coupled to said reference clock signal and said control signal, wherein said clock multiplier circuit outputs said internal clock signal with a frequency determined by said control signal, wherein said frequency of said internal clock signal is equal to the frequency of said reference clock signal upon detecting a first condition of said control signal, and wherein said frequency of said internal clock signal is a multiple of said frequency of said reference clock signal upon detecting a second condition of said control signal, wherein said multiple is not equal to one.

Claim 11

A clock circuit comprising: a clock generator configured to output an external clock signal and a reference clock signal; a phase detector circuit coupled to said external clock signal, an internal clock signal and said reference clock signal and configured to output a control signal and a phase enable signal, wherein said control signal is indicative of a frequency relationship between said external clock signal and said reference clock signal, and wherein said phase enable signal is indicative of a phase relationship between said external clock signal and said internal clock signal; a clock multiplier circuit coupled to said reference clock signal and said control signal, wherein said clock multiplier circuit outputs said internal clock signal with a frequency determined by said control signal, wherein said frequency of said internal clock signal is equal to the frequency of said reference clock signal upon detecting a first condition of said control signal, and wherein said frequency of said internal clock signal is a multiple of said frequency of said reference clock signal upon detecting a second condition of said control signal, wherein said multiple is not equal to one.

Claim 12

The clock circuit of claim 9 wherein said clock multiplier circuit is a phase-locked loop.

Claim 13

The clock circuit of claim 9 wherein said frequency of said internal clock signal is twice said frequency of said reference clock signal if said frequency of said reference clock signal equals said frequency of said external clock signal.

Claim 14

The clock circuit of claim 9 wherein said frequency of said internal clock signal is equal to said frequency of said reference clock signal if said frequency of said reference clock signal is twice said frequency of said external clock signal.

Claim 15

The clock circuit of claim 10 wherein said phase-locked loop comprises: a phase comparator configured to receive said reference clock signal and a feedback signal, and configured to output an error signal indicative of a phase relationship between said reference clock signal and said feed-back signal; a low-pass filter configured to receive said error signal of said phase comparator; a voltage controlled oscillator configured to receive an output of said low-pass filter and output an oscillator signal; a clock divider circuit configured to receive said oscillator signal and said control signal and output said internal clock signal, wherein a number by which said frequency of said clock signal is divided is determined by said control signal; and a feedback circuit coupled to receive said internal clock signal and output said feedback signal.

Claim 16

A computer system comprising: an integrated processor coupled a clock generator circuit; a peripheral bus coupled to said integrated processor; a peripheral device coupled to said peripheral bus; wherein said integrated processor is configured to receive a reference clock signal and an external clock signal and includes: a processor core, a peripheral bus interface coupled to said processor core; and a clock circuit coupled to said processor core; wherein said processor core, peripheral bus interface, and clock circuit are formed on a single monolithic substrate; wherein said clock circuit is configured to compare a frequency of said reference clock signal to a frequency of said external clock signal and to output an internal clock signal, wherein said clock circuit is configured to generate said internal clock signal with a frequency equal to said frequency of said reference clock signal in response to detecting a first frequency relationship between said reference clock signal and said external clock signal, and wherein said clock circuit is configured to generate said internal clock signal with a frequency which is a multiple of said frequency of said reference clock signal in response to detecting a second frequency relationship between said reference clock signal and said external clock signal, wherein said multiple is not equal to one; wherein said clock circuit comprises a comparator circuit that compares said frequency of said reference clock signal to said frequency of said external clock signal and outputs a control signal indicative of whether said frequency of said reference clock signal equals said frequency of said external clock signal; and a phase-locked loop configured to receive said control signal of said comparator circuit and said reference clock signal and configured to output said internal clock signal.

Claim 17

A computer system comprising: an integrated processor coupled a clock generator circuit; a peripheral bus coupled to said integrated processor; a peripheral device coupled to said peripheral bus; wherein said integrated processor is configured to receive a reference clock signal and an external clock signal and includes: a processor core, a peripheral bus interface coupled to said processor core; and a clock circuit coupled to said processor core; wherein said processor core, peripheral bus interface, and clock circuit are formed on a single monolithic substrate; wherein said clock circuit is configured to compare a frequency of said reference clock signal to a frequency of said external clock signal and to output an internal clock signal, wherein said clock circuit is configured to generate said internal clock signal with a frequency equal to said frequency of said reference clock signal in response to detecting a first frequency relationship between said reference clock signal and said external clock signal, and wherein said clock circuit is configured to generate said internal clock signal with a frequency which is a multiple of said frequency of said reference clock signal in response to detecting a second frequency relationship between said reference clock signal and said external clock signal, wherein said multiple is not equal to one; wherein said clock circuit comprises a comparator circuit that compares said frequency of said reference clock signal to said frequency of said external clock signal and outputs a control signal indicative of whether said frequency of said reference clock signal equals said frequency of said external clock signal; and a phase-locked loop configured to receive said control signal of said comparator circuit and said reference clock signal and configured to output said internal clock signal.

Claim 18

The computer system of claim 14 wherein said multiple of said frequency of said reference clock signal is twice said frequency of said reference clock signal.

Claim 19

The computer system of claim 15 wherein said frequency of said internal clock signal is twice said frequency of said reference clock signal in response to said comparison detecting said frequency of said reference clock signal equals said frequency of said external clock signal.

Claim 20

The computer system of claim 15 wherein said frequency of said internal clock signal is equal to said frequency of said reference clock signal in response to said comparison detecting said frequency of said reference clock signal is twice said frequency of said external clock signal.

Claim 21

The computer system of claim 14 wherein said clock circuit is coupled to said peripheral bus interface and said internal clock signal provides a timing signal to said peripheral bus interface.

Claim 22

The computer system of claim 14 wherein said phase-locked loop comprises: a phase comparator configured to receive said reference clock signal and a feedback signal, and configured to output an error signal indicative of a phase relationship between said reference clock signal and said feedback signal; a low-pass filter configured to receive said error signal of said phase comparator; a voltage controlled oscillator configured to receive an output of said low-pass filter and output an oscillator signal; a clock divider circuit configured to receive said oscillator signal and said control signal and output said internal clock signal, wherein a number by which said frequency of said clock signal is divided is determined by said control signal; and a feedback circuit coupled to receive said internal clock signal and output said feedback signal.