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US6084807A
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Memory device with global redundancy
Assignee: SK Hynix Inc
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Filing: 1999-11-08
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Granted: 2000-07-04
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Expires: 2019-11-08
Abstract
Abstract A memory device with global redundancy repair architecture and method of employing same. In the memory device containing blocks of normal memory cells, redundant cells are assembled in one block called a special block. One or more sense amplifiers are coupled to each block, including the special block. The sense amplifiers connected to the special block are not shared between the special block and a neighboring normal block or any other normal block. Addresses of defective cells are stored in fuse boxes that assign the defective address to a repair cell within the special block. The fuse boxes can assign any normal cell in the array to a repair cell in the special block. In the method, a selected memory block is operated whether the selected word line needs repair or not without waiting for a comparison signal from the fuse box. The special block is always operated as if it is selected. If a block adjacent the special block is selected, there is no problem since the special block does not share a sense amp with adjacent blocks. Since the block containing the repair cells is always turned on, toggling of the sense amps and consequent current is greatly reduced.
Inventors
- 👤 Jin H. Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:32
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/808; G11C29/83; G11C29/84; H; H10; H10D; H10D84/00
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
123 words
A memory device with global redundancy, comprising: a plurality of blocks of memory each having an array of normal memory cells, one block of the plurality of blocks being a special block, the special block further having an array of redundant memory cells; and a plurality of banks of sense amplifiers disposed adjacent the plurality of blocks of memory and coupled to the plurality of blocks of memory such that except for the special block, other blocks in the plurality share a bank of sense amplifiers with an adjacent block, wherein, the special block couples to a dedicated bank of sense amplifiers and, wherein, the redundant memory cells can replace defective normal memory cells in any one of the plurality of memory blocks.
Claim 2
Dependent Claim
123 words
A memory device with global redundancy, comprising: a plurality of blocks of memory each having an array of normal memory cells, one block of the plurality of blocks being a special block, the special block further having an array of redundant memory cells; and a plurality of banks of sense amplifiers disposed adjacent the plurality of blocks of memory and coupled to the plurality of blocks of memory such that except for the special block, other blocks in the plurality share a bank of sense amplifiers with an adjacent block, wherein, the special block couples to a dedicated bank of sense amplifiers and, wherein, the redundant memory cells can replace defective normal memory cells in any one of the plurality of memory blocks.
Claim 3
Dependent Claim
56 words
The memory device of claim 1, wherein the plurality of redundant memory cells in the special block are arranged in a plurality of redundant word lines and the plurality of normal cells in each of the blocks and the plurality of normal cells in the special block are arranged in a plurality of normal word lines.
Claim 4
Dependent Claim
29 words
The memory device of claim 2, wherein said plurality of normal wordlines comprises a first plurality of natural main word lines and a second plurality of normal sub-word lines.
Claim 5
Dependent Claim
29 words
The memory device of claim 2, wherein said plurality of redundant wordlines comprises a first plurality of redundant main word lines and a second plurality of redundant sub-word lines.
Claim 6
Dependent Claim
52 words
The memory device of claim 2, further comprising a plurality of fuse boxes, wherein each fuse box in the plurality of fuse boxes is configured to selectively assign a defective address located in any of the blocks of memory to a selected one of the redundant word lines in the special block.
Claim 7
Dependent Claim
69 words
The memory device of claim 2, further comprising a plurality of bit lines configured such that an address of each of the normal memory cells corresponds to an intersection between one of the bit lines and one of the normal word lines and an address of each of the redundant memory cells corresponds to an intersection between one of the bit lines and one of the redundant word lines.
Claim 8
Dependent Claim
44 words
The memory device of claim 6, further comprising a bit line decoder coupled to the plurality of bit lines, wherein the special block is situated closer to the bit line decoder than any of the other blocks of memory in the plurality of blocks.
Claim 9
Dependent Claim
43 words
The memory device of claim 2, further comprising: a word line address decoder coupled to the plurality of normal word lines or the plurality of redundant word lines or both said plurality of normal word lines and the plurality of redundant word lines.
Claim 10
Dependent Claim
33 words
The memory device of claim 1, further comprising: a plurality of block equalizers, wherein each block equalizer is connected to at least one block of memory in the plurality of blocks of memory.
Claim 11
Dependent Claim
18 words
The memory device of claim 1, wherein said memory device is a synchronous dynamic random access memory (SDRAM).
Claim 12
Dependent Claim
18 words
The memory device of claim 10, wherein said synchronous dynamic random access memory is a 256 Megabyte SDRAM.
Claim 13
Independent Claim
87 words
A method of operating a memory device with global redundancy, comprising: providing a plurality of blocks of memory each block having an array of normal memory cells, one block of the plurality of blocks being a special block, the special block further having an array of redundant memory cells; and coupling a plurality of banks of sense amplifiers to the plurality of blocks of memory such that except for the special block, other blocks in the plurality share a bank of sense amplifiers with an adjacent block.
Claim 14
Independent Claim
87 words
A method of operating a memory device with global redundancy, comprising: providing a plurality of blocks of memory each block having an array of normal memory cells, one block of the plurality of blocks being a special block, the special block further having an array of redundant memory cells; and coupling a plurality of banks of sense amplifiers to the plurality of blocks of memory such that except for the special block, other blocks in the plurality share a bank of sense amplifiers with an adjacent block.
Claim 15
Dependent Claim
27 words
The method of claim 12, wherein a block equalizer, connected to at least one of said plurality of normal blocks is turned off prior to said coupling.
Claim 16
Dependent Claim
21 words
The method of claim 12, wherein a block equalizer connected to said special block is turned off prior to said coupling.
Claim 17
Dependent Claim
23 words
The method of claim 12, further comprising: performing a read operation or a write operation on a memory cell in the special block.
Claim 18
Dependent Claim
24 words
The method of claim 12, further comprising: performing a read operation or a write operation on a memory cell in a selected normal block.
Claim 19
Independent Claim
86 words
A method of operating a memory device having a plurality of normal blocks of memory cells and a special block of memory cells, the special block further having a plurality of redundant cells, the method comprising: decoding an input address signal; activating the special block; determining whether the input address selects a block other than the special block; if the input address selects a block other than the special block, activating a selected normal block; and determining whether the decoded address includes a defective memory cell.
Claim 20
Independent Claim
86 words
A method of operating a memory device having a plurality of normal blocks of memory cells and a special block of memory cells, the special block further having a plurality of redundant cells, the method comprising: decoding an input address signal; activating the special block; determining whether the input address selects a block other than the special block; if the input address selects a block other than the special block, activating a selected normal block; and determining whether the decoded address includes a defective memory cell.
Claim 21
Dependent Claim
44 words
The method of claim 17, further comprising: if the decoded address includes a defective memory cell, setting the normal block to a pre-charge state; and performing a read or write operation on one or more of the redundant memory cells in the special block.
Claim 22
Dependent Claim
47 words
The method of claim 17 further comprising: if the decoded address does not include a defective memory cell, setting the special block to a pre-charge state; and performing a read or write operation on one or more of the normal memory cells in the selected normal block.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |