US6091089A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Rohm Co Ltd
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Filing: 1998-10-20
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Granted: 2000-07-18
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Expires: 2018-10-20
Abstract
Abstract A semiconductor integrated circuit device has a semiconductor chip, on which are formed a plurality of input/output circuits and input/output pads individually connected electrically thereto. The input/output pads are connected electrically to a plurality of inner leads formed on the frame on which the semiconductor chip is mounted. The input/output circuits are arranged in two rows along each edge of the semiconductor chip, with the first row of input/output circuits arranged closer to the edge than the second row of input/output circuits. The input/output pads connected to the first-row input/output circuits are arranged in two rows in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits. The input/output pads connected to the second-row input/output circuits are arranged to form a third row of input/output pads along the second row of input/output circuits.
Inventors
- 👤 Noriaki Hiraga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:53
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/5366; H10W72/541; H10W72/5449; H10W72/547; H10W72/931; H10W72/932; H10W72/951; H10W90/00; H10W90/701; H10W90/751; H10W90/754; H10W90/756
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
100 words
A semiconductor integrated circuit device comprising: input/output circuits arranged to form a first and a second row of input/output circuits along each edge of a semiconductor chip; input/output pads connected to the input/output circuits of the first row and arranged to form a first and a second row of input/output pads in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits; and input/output pads connected to the input/output circuits of the second row and arranged to form a third row of input/output pads along the second row of input/output circuits.
Claim 2
Dependent Claim
100 words
A semiconductor integrated circuit device comprising: input/output circuits arranged to form a first and a second row of input/output circuits along each edge of a semiconductor chip; input/output pads connected to the input/output circuits of the first row and arranged to form a first and a second row of input/output pads in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits; and input/output pads connected to the input/output circuits of the second row and arranged to form a third row of input/output pads along the second row of input/output circuits.
Claim 3
Dependent Claim
36 words
A semiconductor integrated circuit device as claimed in claim 1, wherein the input/output circuits of the first row are formed closer to the edge of the semiconductor chip than the input/output circuits of the second row.
Claim 4
Dependent Claim
36 words
A semiconductor integrated circuit device as claimed in claim 2, wherein the input/output pads of the first row are arranged closer to the edge of the semiconductor chip than the input/output pads of the second row.
Claim 5
Dependent Claim
73 words
A semiconductor integrated circuit device as claimed in claim 3, wherein spaces are secured between adjacent input/output circuits of the second row, between adjacent input/output pads of the third row, and between adjacent input/output pads of the second row, so that wires connecting the input/output circuits of the first row to logic circuit elements formed in a central portion of the semiconductor chip will be so arranged as to pass through those spaces.
Claim 6
Dependent Claim
131 words
A semiconductor integrated circuit device comprising: input/output circuits arranged to form a first and a second row of input/output circuits along each edge of a semiconductor chip; input/output pads connected to the input/output circuits of the first row and arranged to form a first and a second row of input/output pads in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits; input/output pads connected to the input/output circuits of the second row and arranged to form a third row of input/output pads along the second row of input/output circuits; and a frame that constitutes the semiconductor chip, wherein the input/output pads of the first, second, and third rows and inner leads formed on the frame are connected by way of wires.
Claim 7
Dependent Claim
131 words
A semiconductor integrated circuit device comprising: input/output circuits arranged to form a first and a second row of input/output circuits along each edge of a semiconductor chip; input/output pads connected to the input/output circuits of the first row and arranged to form a first and a second row of input/output pads in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits; input/output pads connected to the input/output circuits of the second row and arranged to form a third row of input/output pads along the second row of input/output circuits; and a frame that constitutes the semiconductor chip, wherein the input/output pads of the first, second, and third rows and inner leads formed on the frame are connected by way of wires.
Claim 8
Dependent Claim
36 words
A semiconductor integrated circuit device as claimed in claim 5, wherein the input/output circuits of the first row are formed closer to the edge of the semiconductor chip than the input/output circuits of the second row.
Claim 9
Dependent Claim
36 words
A semiconductor integrated circuit device as claimed in claim 6, wherein the input/output pads of the first row are arranged closer to the edge of the semiconductor chip than the input/output pads of the second row.
Claim 10
Dependent Claim
73 words
A semiconductor integrated circuit device as claimed in claim 7, wherein spaces are secured between adjacent input/output circuits of the second row, between adjacent input/output pads of the third row, and between adjacent input/output pads of the second row, so that wires connecting the input/output circuits of the first row to logic circuit elements formed in a central portion of the semiconductor chip will be so arranged as to pass through those spaces.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |