Patent US6091640A successfully refreshed from Google Patents.
US6091640A
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Semiconductor integrated circuit with multiple write operation modes
Assignee: Renesas Electronics Corp
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Filing: 1997-09-30
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Granted: 2000-07-18
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Expires: 2017-09-30
Abstract
Abstract A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
Inventors
- 👤 Takayuki Kawahara
- 👤 Hiroshi Sato
- 👤 Atsushi Nozoe
- 👤 Keiichi Yoshida
- 👤 Satoshi Noda
- 👤 Shoji Kubono
- 👤 Hiroaki Kotani
- 👤 Katsutaka Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:45
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/04; G11C16/0483; G11C16/34; G11C16/3404; G11C16/3436; G11C16/3454; G11C16/3459; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/564; G11C2211/5641
Claims Analysis
Total Claims: 51
Claim 1
Independent Claim
230 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells each of which has one of an erase threshold voltage region corresponding to an erase state and a write threshold voltage region corresponding to a write state; and a control circuit which controls to apply a first pulse-shaped voltage to a memory cell of said plurality of non-volatile memory cells in a first write operation mode, and a second pulse-shaped voltage to a memory cell of said plurality of non-volatile memory cells in a second write operation mode, wherein a threshold voltage of said memory cell in said plurality of non-volatile memory cells changes to a first write threshold voltage region from said erase threshold voltage region in accordance with said first write operation mode, and a threshold voltage of said memory cell in said plurality of non-volatile memory cells changes to a second write threshold voltage region from said erase threshold voltage region in accordance with said second write operation, wherein each of said first and said second write operation modes is set by data or a command which is applied to said control circuit, and wherein the amount of change in threshold voltage of the memory cell applied with said first pulse-shaped voltage is larger than the amount of change in threshold voltage of the memory cell applied with said second pulse-shaped voltage.
Claim 2
Dependent Claim
230 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells each of which has one of an erase threshold voltage region corresponding to an erase state and a write threshold voltage region corresponding to a write state; and a control circuit which controls to apply a first pulse-shaped voltage to a memory cell of said plurality of non-volatile memory cells in a first write operation mode, and a second pulse-shaped voltage to a memory cell of said plurality of non-volatile memory cells in a second write operation mode, wherein a threshold voltage of said memory cell in said plurality of non-volatile memory cells changes to a first write threshold voltage region from said erase threshold voltage region in accordance with said first write operation mode, and a threshold voltage of said memory cell in said plurality of non-volatile memory cells changes to a second write threshold voltage region from said erase threshold voltage region in accordance with said second write operation, wherein each of said first and said second write operation modes is set by data or a command which is applied to said control circuit, and wherein the amount of change in threshold voltage of the memory cell applied with said first pulse-shaped voltage is larger than the amount of change in threshold voltage of the memory cell applied with said second pulse-shaped voltage.
Claim 3
Dependent Claim
59 words
A semiconductor integrated circuit according to claim 1, wherein said control circuit has a rewrite control circuit, and wherein a width of said second write threshold voltage region formed by said first write operating mode is narrower than a width of said second write threshold voltage region formed by said second write operating mode by said rewrite control circuit.
Claim 4
Dependent Claim
56 words
A semiconductor integrated circuit according to claim 1, further comprising a verify level generating circuit which generates a first write verify level in said first write operation mode and which generates a second write verify level in said second write operation mode, wherein said first write verify level is higher than said second write verify level.
Claim 5
Dependent Claim
34 words
A semiconductor integrated circuit according to claim 3, wherein the data written in said first write operation mode is binary data and the data written in said second write operation mode is multivalued data.
Claim 6
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 4, wherein said rewrite control means rewrites binary data written in said first write operation mode to multivalued data in said second write operation mode.
Claim 7
Dependent Claim
46 words
A semiconductor integrated circuit according to claim 5, wherein a first memory mat in which data is written in said first write operation mode, and a second memory mat in which data is written in said second write operation mode, are respectively provided in separate form.
Claim 8
Dependent Claim
46 words
A semiconductor integrated circuit according to claim 3, wherein a first memory mat in which data is written in said first write operation mode, and a second memory mat in which data is written in said second write operation mode, are respectively provided in separate form.
Claim 9
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 7, further including a trimming circuit capable of trimming the minimum value of said each pulse-shaped voltage.
Claim 10
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 8, wherein said trimming circuit is further capable of trimming the rate of gradual increase in said each pulse-shaped voltage.
Claim 11
Dependent Claim
34 words
A semiconductor integrated circuit according to claim 1, wherein the data written in said first write operation mode is binary data and the data written in said second write operation mode is multivalued data.
Claim 12
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 10, wherein said rewrite control means rewrites binary data written in said first write operation mode to multivalued data in said second write operation mode.
Claim 13
Dependent Claim
46 words
A semiconductor integrated circuit according to claim 11, wherein a first memory mat in which data is written in said first write operation mode, and a second memory mat in which data is written in said second write operation mode, are respectively provided in separate form.
Claim 14
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 11, further including a trimming circuit capable of trimming the minimum value of the pulse width of said each pulse-shaped voltage.
Claim 15
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 13, wherein said trimming circuit is further capable of trimming the rate of gradual increase in pulse width of said each pulse-shaped voltage.
Claim 16
Dependent Claim
46 words
A semiconductor integrated circuit according to claim 1, wherein a first memory mat in which data is written in said first write operation mode, and a second memory mat in which data is written in said second write operation mode, are respectively provided in separate form.
Claim 17
Dependent Claim
45 words
A semiconductor integrated circuit according to claim 1, wherein, upon said first and second write operation modes, said control circuits fixes values of pulse-shaped voltages and varies the amount of change in threshold voltage according to the difference between pulse widths of the pulse-shaped voltages.
Claim 18
Dependent Claim
45 words
A semiconductor integrated circuit according to claim 1, wherein, upon said first and second write operation modes, said control circuit fixes pulse widths of pulse-shaped voltages and varies the amount of change in threshold voltage according to the difference between values of the pulse-shaped voltages.
Claim 19
Dependent Claim
86 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means controlling the second threshold voltage to a voltage lying within a range lower than or equal to a power source voltage and higher than or equal to one half the power source voltage.
Claim 20
Dependent Claim
86 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means controlling the second threshold voltage to a voltage lying within a range lower than or equal to a power source voltage and higher than or equal to one half the power source voltage.
Claim 21
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 18, wherein said control means sets the amount of change in threshold voltage per pulse-shaped voltage to above 0.4V.
Claim 22
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 18, wherein said control means sets the amount of change in threshold voltage per pulse-shaped voltage to above one third the difference between the first threshold voltage and the second threshold voltage.
Claim 23
Dependent Claim
82 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means controlling the second threshold voltage to a voltage lying within a range from below 3.3V to above 2V when a power source voltage is in the neighborhood of 3.3V.
Claim 24
Dependent Claim
82 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means controlling the second threshold voltage to a voltage lying within a range from below 3.3V to above 2V when a power source voltage is in the neighborhood of 3.3V.
Claim 25
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 21, wherein said control means sets the amount of change in threshold voltage per pulse-shaped voltage to above 0.4V.
Claim 26
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 21, wherein said control means sets the amount of change in threshold voltage per pulse-shaped voltage to above one third the difference between the first threshold voltage and the second threshold voltage.
Claim 27
Dependent Claim
128 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; and wherein a control voltage for turning on a non-selected non-volatile memory cell is supplied to the non-selected non-volatile memory cell upon an read operation, said control means controlling the second threshold voltage so as to reach a voltage lying within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to the control voltage and is higher than or equal to one half a power source voltage.
Claim 28
Dependent Claim
128 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; and wherein a control voltage for turning on a non-selected non-volatile memory cell is supplied to the non-selected non-volatile memory cell upon an read operation, said control means controlling the second threshold voltage so as to reach a voltage lying within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to the control voltage and is higher than or equal to one half a power source voltage.
Claim 29
Dependent Claim
121 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; and wherein a control voltage for turning on a non-selected non-volatile memory cell is supplied to the non-selected non-volatile memory cell upon a read operation, said control means controlling the second threshold voltage so as to reach a voltage lying within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to 3.3V and is higher than or equal to 2V.
Claim 30
Dependent Claim
121 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; and wherein a control voltage for turning on a non-selected non-volatile memory cell is supplied to the non-selected non-volatile memory cell upon a read operation, said control means controlling the second threshold voltage so as to reach a voltage lying within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to 3.3V and is higher than or equal to 2V.
Claim 31
Dependent Claim
124 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein said control means has rewrite control means for rewriting data written in said first operating mode in said second operating mode.
Claim 32
Dependent Claim
124 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein said control means has rewrite control means for rewriting data written in said first operating mode in said second operating mode.
Claim 33
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 26, wherein a first memory mat in which data is written in said first operating mode, and a second memory mat in which data is written in said second operating mode, are respectively provided in separate form.
Claim 34
Dependent Claim
23 words
A semiconductor integrated circuit according to claim 27, further including trimming means capable of trimming the minimum value of said each pulse-shaped voltage.
Claim 35
Dependent Claim
165 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein a second threshold voltage of said memory cell which is obtained by said first operating mode is higher than or equal to a second threshold voltage of said memory cell which is obtained by said second operating mode, wherein the data written in said first operating mode is binary data and the data written in said second operating mode is multivalued data.
Claim 36
Dependent Claim
165 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein a second threshold voltage of said memory cell which is obtained by said first operating mode is higher than or equal to a second threshold voltage of said memory cell which is obtained by said second operating mode, wherein the data written in said first operating mode is binary data and the data written in said second operating mode is multivalued data.
Claim 37
Dependent Claim
34 words
A semiconductor integrated circuit according to claim 29, wherein said control means has rewrite control means which rewrites binary data written in said first operating mode to multivalued data in said second operating mode.
Claim 38
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 30, wherein a first memory mat in which data is written in said first operating mode, and a second memory mat in which data is written in said second operating mode, are respectively provided in separate form.
Claim 39
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 31, wherein said trimming means is further capable of trimming the rate of gradual increase in pulse width of said each pulse-shaped voltage.
Claim 40
Dependent Claim
153 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein a level to be written into said memory cell in said first operating mode is higher than or equal to that in said second operating mode; wherein the data written in said first operating mode is binary data and the data written in said second operating mode is multivalued data.
Claim 41
Dependent Claim
153 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein a level to be written into said memory cell in said first operating mode is higher than or equal to that in said second operating mode; wherein the data written in said first operating mode is binary data and the data written in said second operating mode is multivalued data.
Claim 42
Dependent Claim
34 words
A semiconductor integrated circuit according to claim 33, wherein said control means has rewrite control means which rewrites binary data written in said first operating mode to multivalued data in said second operating mode.
Claim 43
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 34, wherein a first memory mat in which data is written in said first operating mode, and a second memory mat in which data is written in said second operating mode, are respectively provided in separate form.
Claim 44
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 34, further including trimming means capable of trimming the minimum value of the pulse width of said each pulse-shaped voltage.
Claim 45
Dependent Claim
138 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein a first memory mat in which data is written in said first operating mode, and a second memory mat in which data is written in said second operating mode, are respectively provided in separate form.
Claim 46
Dependent Claim
138 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein a first memory mat in which data is written in said first operating mode, and a second memory mat in which data is written in said second operating mode, are respectively provided in separate form.
Claim 47
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 37, wherein said trimming means is further capable of trimming the rate of gradual increase in said each pulse-shaped voltage.
Claim 48
Dependent Claim
138 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein, upon said first and second operating modes, said control means fixes values of pulse-shaped voltages and varies the amount of change in threshold voltage according to the difference between pulse widths of the pulse-shaped voltages.
Claim 49
Dependent Claim
138 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein, upon said first and second operating modes, said control means fixes values of pulse-shaped voltages and varies the amount of change in threshold voltage according to the difference between pulse widths of the pulse-shaped voltages.
Claim 50
Dependent Claim
138 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein, upon said first and second operating modes, said control means fixes pulse widths of pulse-shaped voltages and varies the amount of change in threshold voltage according to the difference between values of the pulse-shaped voltages.
Claim 51
Dependent Claim
138 words
A semiconductor integrated circuit comprising: a plurality of electrically erasable and programmable non-volatile memory cells; and control means for supplying a pulse-shaped voltage to said each non-volatile memory cell until a threshold voltage of said non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage; said control means having a first operating mode in which the amount of change in threshold voltage of said non-volatile memory cell, which varies each time said pulse-shaped voltage is applied thereto, is larger than the amount of change in threshold voltage of said non-volatile memory cell in a second operating mode; wherein, upon said first and second operating modes, said control means fixes pulse widths of pulse-shaped voltages and varies the amount of change in threshold voltage according to the difference between values of the pulse-shaped voltages.
References Cited (Backward Citations)
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