US6094065A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with field programmable and application specific logic areas
Assignee: Xilinx Inc
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Filing: 1998-10-20
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Granted: 2000-07-25
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Expires: 2018-10-20
Abstract
Abstract A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.
Inventors
- 👤 Danesh Tavana
- 👤 Wilson K. Yee
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:38
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/1778; H03K19/17796
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-defined gates having permanent customized functions and connection relationships; a plurality of externally accessible signal connections coupled to said arrays of programmable gates and mask-defined gates, said externally accessible signal connections comprising arrays of programmable and mask-defined interconnections; a plurality of input/output pads coupled to said plurality of externally accessible signal connections; and a plurality of first interconnections between said arrays of programmable gates and mask-defined gates.
Claim 2
Dependent Claim
107 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-defined gates having permanent customized functions and connection relationships; a plurality of externally accessible signal connections coupled to said arrays of programmable gates and mask-defined gates, said externally accessible signal connections comprising arrays of programmable and mask-defined interconnections; a plurality of input/output pads coupled to said plurality of externally accessible signal connections; and a plurality of first interconnections between said arrays of programmable gates and mask-defined gates.
Claim 3
Dependent Claim
68 words
The integrated circuit recited in claim 1 wherein said plurality of externally accessible signal connections comprise a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectable intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.
Claim 4
Dependent Claim
32 words
The integrated circuit recited in claim 1 further comprising a plurality of externally accessible clock connections coupled between a plurality of clock pads and said arrays of programmable gates and mask-defined gates.
Claim 5
Dependent Claim
31 words
The integrated circuit recited in claim 3 wherein at least one of said plurality of clock pads is programmably connectable to both of said arrays of programmable gates and mask-defined gates.
Claim 6
Dependent Claim
107 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-programmed gates having permanent customized functions and connection relationships; a plurality of externally accessible signal connections coupled to said arrays of programmable gates and mask-programmed gates, said externally accessible signal connections comprising arrays of programmable and mask-programmed interconnections; a plurality of input/output pads coupled to said plurality of externally accessible signal connections; and a plurality of first interconnections between said arrays of programmable gates and mask-programmed gates.
Claim 7
Dependent Claim
107 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-programmed gates having permanent customized functions and connection relationships; a plurality of externally accessible signal connections coupled to said arrays of programmable gates and mask-programmed gates, said externally accessible signal connections comprising arrays of programmable and mask-programmed interconnections; a plurality of input/output pads coupled to said plurality of externally accessible signal connections; and a plurality of first interconnections between said arrays of programmable gates and mask-programmed gates.
Claim 8
Dependent Claim
67 words
The integrated circuit recited in claim 5 wherein said plurality of accessible signal connections comprise a first matrix of field programmable interconnections and a second matrix of mask-programmed permanent interconnections, said first matrix and said second matrix each having a plurality of selectable intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.
Claim 9
Dependent Claim
32 words
The integrated circuit recited in claim 5 further comprising a plurality of externally accessible clock connections coupled between a plurality of clock pads and said arrays of programmable gates and mask-programmed gates.
Claim 10
Dependent Claim
31 words
The integrated circuit recited in claim 7 wherein at least one of said plurality of clock pads is programmably connectable to both of said arrays of programmable gates and mask-programmed gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-25 | 2004-01-24 | 2004-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-25 | 2008-01-24 | 2008-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-25 | 2012-01-24 | 2012-07-25 | $7700.00 | Window Closed / Lapsed |