US5682106A
Expired / Lapsed
US
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Logic module for field programmable gate array
Assignee: QuickLogic Corp
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Filing: 1996-09-18
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Granted: 1997-10-28
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Expires: 2016-09-18
Abstract
Abstract A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.
Inventors
- 👤 William D. Cox
- 👤 Benjamin W. Blair
- 👤 Paige A. Kolze
- 👤 Hua-Thye Chua
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17758; G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
203 words
A field programmable gate array, comprising: a programmable interconnect structure; and a plurality of logic modules, each of said logic modules comprising: a first combinatorial logic circuit having five input leads and an output lead, each of said input leads and said output lead extending from said logic module and into said programmable interconnect structure; a second combinatorial logic circuit having six input leads and an output lead, five of said input leads and said output lead extending from said logic module and into said programmable interconnect structure, one of said input leads not extending from said logic module; and a first multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead being directly connected to said output lead of said first combinatorial logic circuit within said logic module, said second data input lead extending from said logic module and into said programmable interconnect structure, said select input lead extending from said logic module and into said programmable interconnect structure, said output lead of said first multiplexer being directly connected to said input lead of said second combinatorial logic circuit which does not extend from said logic module.
Claim 2
Dependent Claim
203 words
A field programmable gate array, comprising: a programmable interconnect structure; and a plurality of logic modules, each of said logic modules comprising: a first combinatorial logic circuit having five input leads and an output lead, each of said input leads and said output lead extending from said logic module and into said programmable interconnect structure; a second combinatorial logic circuit having six input leads and an output lead, five of said input leads and said output lead extending from said logic module and into said programmable interconnect structure, one of said input leads not extending from said logic module; and a first multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead being directly connected to said output lead of said first combinatorial logic circuit within said logic module, said second data input lead extending from said logic module and into said programmable interconnect structure, said select input lead extending from said logic module and into said programmable interconnect structure, said output lead of said first multiplexer being directly connected to said input lead of said second combinatorial logic circuit which does not extend from said logic module.
Claim 3
Dependent Claim
34 words
The field programmable gate array of claim 1, wherein a signal passing from said first combinatorial logic circuit to said second combinatorial logic circuit via said first multiplexer does not pass through any antifuses.
Claim 4
Dependent Claim
25 words
The field programmable gate array of claim 1, wherein said first combinatorial logic circuit has an additional input lead which extends from said logic module.
Claim 5
Dependent Claim
20 words
The field programmable gate array of claim 1, wherein said first combinatorial logic circuit is a six input AND gate.
Claim 6
Dependent Claim
97 words
The field programmable gate array of claim 1, wherein said second combinatorial logic circuit comprises: a second multiplexer having a first data input lead, a second data input lead, a select input lead, an output lead; a third multiplexer having a first data input lead, a second data input lead, a select input lead, an output lead; and a fourth multiplexer having a first data input lead coupled to said output lead of said second multiplexer, a second data input lead coupled to said output lead of said third multiplexer, a select input lead, an output lead.
Claim 7
Dependent Claim
28 words
The field programmable gate array of claim 5, wherein said output lead of said first multiplexer is directly connected to said select input lead of said second multiplexer.
Claim 8
Dependent Claim
194 words
The field programmable gate array of claim 1, wherein said second combinatorial logic circuit in each of said plurality of logic modules has an additional input lead which does not extend from said logic module, and wherein each of said logic modules further comprises: a third combinatorial logic circuit having five input leads and an output lead, each of said input leads and said output lead extending from said logic module and into said programmable interconnect structure; and a second multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead of said second multiplexer being directly connected to said output lead of said third combinatorial logic circuit within said logic module, said second data input lead of said second multiplexer extending from said logic module and into said programmable interconnect structure, said select input lead of said second multiplexer extending from said logic module and into said programmable interconnect structure, said output lead of said second multiplexer being directly connected to said additional input lead of said second combinatorial logic circuit which does not extend from said logic module.
Claim 9
Dependent Claim
55 words
The field programmable gate array of claim 1, wherein each of said logic modules further comprises: a sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said sequential logic element being coupled to said output lead of said second combinatorial logic circuit.
Claim 10
Dependent Claim
121 words
The field programmable gate array of claim 5, wherein said second combinatorial logic circuit further comprises: a fifth multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead of said fifth multiplexer being directly connected to said output lead of said first combinatorial logic circuit within said logic module, said second data input lead of said fifth multiplexer extending from said logic module and into said programmable interconnect structure, said select input lead of said fifth multiplexer extending from said logic module and into said programmable interconnect structure, said output lead of said fifth multiplexer being directly connected to said select input of said third multiplexer.
Claim 11
Dependent Claim
300 words
A field programmable gate array, comprising: an interconnect structure; and a plurality of logic modules, each of said logic modules comprising: a first combinatorial logic circuit having five input leads and an output lead O1, each of said input leads and said output lead O1 extending from said logic module and into said interconnect structure; a second combinatorial logic circuit having seven input leads and an output lead, five of said input leads and said output lead extending from said logic module and into said interconnect structure, two of said input leads I1 and I2 not extending from said logic module; a third combinatorial logic circuit having five input leads and an output lead O2, each of said input leads and said output lead O2 extending from said logic module and into said interconnect structure; first means for selectively coupling said output lead O1 to said input lead I1 such that a signal passing from said output lead O1 to said input lead I1 passes through no permanently programmed element, said first means also being for selectively decoupling said output lead O1 from said input lead I1 such that said second combinatorial logic circuit can be used independently of said first combinatorial logic circuit without said input lead I1 being permanently driven with one digital logic value; and second means for selectively coupling said output lead O2 to said input lead I2 such that a signal passing from said output lead O2 to said input lead I2 passes through no permanently programmed element, said second means also being for selectively decoupling said output lead O2 from said input lead I2 such that said second combinatorial logic circuit can be used independently of said first combinatorial logic circuit without said input lead I2 being permanently driven with one digital logic value.
Claim 12
Dependent Claim
300 words
A field programmable gate array, comprising: an interconnect structure; and a plurality of logic modules, each of said logic modules comprising: a first combinatorial logic circuit having five input leads and an output lead O1, each of said input leads and said output lead O1 extending from said logic module and into said interconnect structure; a second combinatorial logic circuit having seven input leads and an output lead, five of said input leads and said output lead extending from said logic module and into said interconnect structure, two of said input leads I1 and I2 not extending from said logic module; a third combinatorial logic circuit having five input leads and an output lead O2, each of said input leads and said output lead O2 extending from said logic module and into said interconnect structure; first means for selectively coupling said output lead O1 to said input lead I1 such that a signal passing from said output lead O1 to said input lead I1 passes through no permanently programmed element, said first means also being for selectively decoupling said output lead O1 from said input lead I1 such that said second combinatorial logic circuit can be used independently of said first combinatorial logic circuit without said input lead I1 being permanently driven with one digital logic value; and second means for selectively coupling said output lead O2 to said input lead I2 such that a signal passing from said output lead O2 to said input lead I2 passes through no permanently programmed element, said second means also being for selectively decoupling said output lead O2 from said input lead I2 such that said second combinatorial logic circuit can be used independently of said first combinatorial logic circuit without said input lead I2 being permanently driven with one digital logic value.
Claim 13
Dependent Claim
43 words
The field programmable gate array of claim 10, wherein said first means has an input lead, and wherein programming an antifuse coupled to said input lead of said first means causes said output lead O1 to be coupled to said input lead I1.
Claim 14
Dependent Claim
43 words
The field programmable gate array of claim 10, wherein said first means has an input lead, and wherein programming an antifuse coupled to said input lead of said first means causes said output lead O1 to be decoupled from said input lead I1.
Claim 15
Dependent Claim
46 words
The field programmable gate array of claim 10, wherein each of said logic modules further comprises: a sequential logic element having a data input lead directly connected within said logic module to an output lead of one of said first, second and third combinatorial logic circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-27 | 2001-04-28 | 2001-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-27 | 2005-04-28 | 2005-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-27 | 2009-04-28 | 2009-10-28 | $7700.00 | Window Closed / Lapsed |