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US6094705A
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Method and system for selective DRAM refresh to reduce power consumption
Assignee: ARM Ltd
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Filing: 1999-03-10
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Granted: 2000-07-25
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Expires: 2019-03-10
Abstract
Abstract A method and system for selective refresh for a memory array is disclosed. The method and system comprises providing a plurality of valid bits, each of the valid bits being associated with a row of the memory device; and detecting when data access is performed within a row of the device. The method and system further comprises setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for the refresh period. By providing the valid bits in the refresh controller and associating them with a row of the memory array then if a cell is written or read at least once a duration equivalent to a refresh period, then the cells do not need to be refreshed. When a DRAM cell is accessed (read or written), its charge is fully restored so that it does not need refresh for a duration equivalent to a refresh interval. In applications that use DRAMs to repeatedly write and read data, such as frame buffers in display systems, the DRAM cells may be accessed frequently enough so that the cells may not need to be refreshed at all. If the cells are written or read at least once in a duration equivalent to a refresh period, then they do not need to be refreshed. Accordingly, through the use of the present invention power consumption is significantly reduced.
Inventors
- 👤 Seungyoon Peter Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
78 words
A method for selective refresh for a memory array comprising the steps of: (a) providing a plurality of valid bits, each of the valid bits being associated with a row of the memory array; (b) detecting when data access is performed within a row of the memory array; and (c) setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for a refresh period.
Claim 2
Independent Claim
78 words
A method for selective refresh for a memory array comprising the steps of: (a) providing a plurality of valid bits, each of the valid bits being associated with a row of the memory array; (b) detecting when data access is performed within a row of the memory array; and (c) setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for a refresh period.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein the memory array comprises a DRAM.
Claim 4
Dependent Claim
14 words
The method of claim 2 wherein the DRAM comprises a plurality of DRAM cells.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein the data access comprises a read operation.
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein the data access comprises a write operation.
Claim 7
Dependent Claim
13 words
The method of claim 1 wherein the data access comprises a refresh operation.
Claim 8
Dependent Claim
18 words
The method of claim 6 which includes the step of clearing the valid bits after a refresh interval.
Claim 9
Independent Claim
90 words
A system for selective refresh of a memory array comprising: a row decoder for detecting when data access occurs to a cell within a row and setting one of a plural of valid bits based upon the data access; and a refresh control means for providing a refresh address to a row decoder of the memory array; the refresh control means including a register, the register including the plurality of valid bits, each of the plurality of valid bits being associated with one of the rows of the memory arrays.
Claim 10
Independent Claim
90 words
A system for selective refresh of a memory array comprising: a row decoder for detecting when data access occurs to a cell within a row and setting one of a plural of valid bits based upon the data access; and a refresh control means for providing a refresh address to a row decoder of the memory array; the refresh control means including a register, the register including the plurality of valid bits, each of the plurality of valid bits being associated with one of the rows of the memory arrays.
Claim 11
Dependent Claim
12 words
The system of claim 8 wherein the memory array comprises a DRAM.
Claim 12
Dependent Claim
14 words
The system of claim 9 wherein the DRAM comprises a plurality of DRAM cells.
Claim 13
Dependent Claim
13 words
The system of claim 8 wherein the data access comprises a read operation.
Claim 14
Dependent Claim
13 words
The system of claim 8 wherein the data access comprises a write operation.
Claim 15
Dependent Claim
13 words
The system of claim 8 wherein the data access comprises a refresh operation.
Claim 16
Dependent Claim
19 words
The system of claim 8 which further comprises a counter for clearing the valid bits after a refresh interval.
Claim 17
Independent Claim
78 words
A system for selective refresh for a memory array comprising: means for providing a plurality of valid bits, each of the valid bits being associated with a row of the memory array; means for detecting when data access is performed within a row of the memory array; and means for setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for a refresh period.
Claim 18
Independent Claim
78 words
A system for selective refresh for a memory array comprising: means for providing a plurality of valid bits, each of the valid bits being associated with a row of the memory array; means for detecting when data access is performed within a row of the memory array; and means for setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for a refresh period.
Claim 19
Dependent Claim
12 words
The system of claim 15 wherein the memory array comprises a DRAM.
Claim 20
Dependent Claim
14 words
The system of claim 16 wherein the DRAM comprises a plurality of DRAM cells.
Claim 21
Dependent Claim
13 words
The system of claim 15 wherein the data access comprises a read operation.
Claim 22
Dependent Claim
13 words
The system of claim 15 wherein the data access comprises a write operation.
Claim 23
Dependent Claim
13 words
The system of claim 15 wherein the data access comprises a refresh operation.
Claim 24
Dependent Claim
17 words
The system of claim 15 which includes means for clearing the valid bit after a refresh interval.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-25 | 2004-01-24 | 2004-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-25 | 2008-01-24 | 2008-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-25 | 2012-01-24 | 2012-07-25 | $7700.00 | Window Closed / Lapsed |