Ram-based associative content-addressable memory device, method of operation thereof and ATM communication switching system employing the same

Claim 2

A memory device, comprising: a validation random access memory (RAM) having a plurality of addressable locations therein, said addressable locations containing validation indicators corresponding to patterns that have been programed into said validation RAM; circuitry, coupled to said validation RAM, that provides an incoming pattern to said validation RAM and retrieves a corresponding validation indicator from said validation RAM, said validation indicator indicating whether said incoming pattern had been programed into said validation RAM; and an association RAM coupled to said circuitry, said circuitry providing said incoming pattern to said association RAM, retrieving a corresponding associative pattern from said association RAM and providing said associative pattern to an output of said memory device only if said validation indicator indicates that said incoming pattern had been programed into said validation RAM.

Claim 3

The device as recited in claim 1 wherein said circuitry provides said incoming pattern to an output of said memory device only if said validation indicator indicates that said incoming pattern had been programed into said validation RAM.

Claim 4

The device as recited in claim 1 wherein said memory device operates in a programing mode in which said circuitry provides a program pattern to said validation RAM and sets a validation indicator in an addressable location in said validation RAM corresponding to said program pattern to a value indicating that said program pattern has been programed into said validation RAM.

Claim 5

The device as recited in claim 1 wherein said memory device operates in a programing mode in which said circuitry provides a program pattern to said validation RAM, provides an associative program pattern to said association RAM, sets a validation indicator in an addressable location in said validation RAM corresponding to said program pattern to a value indicating that said program pattern has been programed into said validation RAM and stores said associative pattern in an addressable location in said association RAM corresponding to said program pattern.

Claim 6

The device as recited in claim 1 wherein said validation RAM and said association RAM are consolidated into a common physical device.

Claim 7

The device as recited in claim 1 wherein said circuitry comprises an error counter, a value of said error counter modified when said validation indicator indicates that said incoming pattern had not been programed into said validation RAM.

Claim 10

The method as recited in claim 7 further comprising providing said incoming pattern to an output of said memory device only if said validation indicator indicates that said incoming pattern had been programed into said validation RAM.

Claim 11

The method as recited in claim 7 further comprising operating said memory device in a programing mode, including: providing a program pattern to said validation RAM; and setting a validation indicator in an addressable location in said validation RAM corresponding to said program pattern to a value indicating that said program pattern has been programed into said validation RAM.

Claim 12

The method as recited in claim 7 further comprising operating said memory device in a programing mode, including: providing a program pattern to said validation RAM; providing an associative program pattern to said association RAM; setting a validation indicator in an addressable location in said validation RAM corresponding to said program pattern to a value indicating that said program pattern has been programed into said validation RAM; and storing said associative pattern in an addressable location in said association RAM corresponding to said program pattern.

Claim 13

The method as recited in claim 7 wherein said validation RAM and said association RAM are consolidated into a common physical device.

Claim 14

The method as recited in claim 7 further comprising modifying a value of an error counter when said validation indicator indicates that said incoming pattern had not been programed into said validation RAM.

Claim 15

An Asynchronous Transfer Mode (ATM) communication switching system, comprising: a port unit that provides an input/output interface for ATM cells received from or transmitted to a communications network; a timing and controller unit that synchronizes and regulates an operation of components associated with said ATM communication switching system; a switching unit that switches said ATM cells through said ATM communication switching system; and a random access memory (RAM), including: a validation portion having a plurality of addressable locations containing validation indicators corresponding to patterns that have been programed into said validation portion, and an association portion having a plurality of addressable locations containing Virtual Path Identifier (VPI) and Virtual Channel Identifier (VCI) associative patterns; and circuitry, coupled to said RAM, that determines whether an incoming pattern, associated with said ATM cell, corresponds to a VPI or a VCI, provides said incoming pattern to said validation portion and retrieves a corresponding validation indicator from said RAM, said validation indicator indicating whether said incoming pattern had been programed into said validation portion, said circuitry retrieving-said VPI or VCI associative pattern from said RAM only if said validation indicator indicates that said incoming pattern had been programed into said validation portion.

Claim 16

An Asynchronous Transfer Mode (ATM) communication switching system, comprising: a port unit that provides an input/output interface for ATM cells received from or transmitted to a communications network; a timing and controller unit that synchronizes and regulates an operation of components associated with said ATM communication switching system; a switching unit that switches said ATM cells through said ATM communication switching system; and a random access memory (RAM), including: a validation portion having a plurality of addressable locations containing validation indicators corresponding to patterns that have been programed into said validation portion, and an association portion having a plurality of addressable locations containing Virtual Path Identifier (VPI) and Virtual Channel Identifier (VCI) associative patterns; and circuitry, coupled to said RAM, that determines whether an incoming pattern, associated with said ATM cell, corresponds to a VPI or a VCI, provides said incoming pattern to said validation portion and retrieves a corresponding validation indicator from said RAM, said validation indicator indicating whether said incoming pattern had been programed into said validation portion, said circuitry retrieving-said VPI or VCI associative pattern from said RAM only if said validation indicator indicates that said incoming pattern had been programed into said validation portion.

Claim 17

The system as recited in claim 13 wherein said circuitry provides, said incoming pattern to an output of said system only if said validation indicator indicates that said incoming pattern had been programed into said validation RAM.

Claim 18

The system as recited in claim 13 wherein said RAM and circuitry operate in a programing mode in which said circuitry provides a program pattern to said validation portion, provides a VPI or VCI associative program pattern to said association portion, sets a validation indicator in an addressable location in said validation portion corresponding to said program pattern to a value indicating that said program pattern has been programed into said validation portion and stores said associative pattern in an addressable location in said association portion corresponding to said program pattern.

Claim 19

The system as recited in claim 13 wherein said validation portion and said association portion are contained in separate physical devices.

Claim 20

The system as recited in claim 13 wherein said circuitry comprises an error counter, a value of said error counter modified when said validation indicator indicates that said incoming pattern had not been programed into said validation portion.

Claim 21

The system as recited in claim 13 further comprising an output register, coupled to said RAM, that temporarily latches said VPI or VCI associative pattern.