US5806083A — Apparatus and method for an improved content addr…

Claim 1

Independent Claim 144 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; inputting a portion of a preselected one of the plurality of data entities as an address for one of the data storage locations to access the data entry stored in a corresponding one of the data storage locations, the data entry including match information corresponding to the portion of the preselected one of the plurality of data entities; and serially inputting to the RAM, as addresses, preselected slices of the portion of the preselected one of the plurality of data entities, one slice per preselected time period.

Claim 2

Independent Claim 144 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; inputting a portion of a preselected one of the plurality of data entities as an address for one of the data storage locations to access the data entry stored in a corresponding one of the data storage locations, the data entry including match information corresponding to the portion of the preselected one of the plurality of data entities; and serially inputting to the RAM, as addresses, preselected slices of the portion of the preselected one of the plurality of data entities, one slice per preselected time period.

Claim 3

Dependent Claim 219 words

A content addressable memory comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address and containing one of a plurality of data entries; each of the data entries including predetermined match information for a portion of one of a plurality of data entities; each portion of each one of the plurality of data entities including said unique address of the data storage location containing the match information for the portion; said RAM having an address port for input of a portion of a first one of the plurality of data entities to the RAM as an address and the RAM operating to fetch the one of the plurality of data entries stored at said address; and said RAM having an output for output of match information corresponding to the portion of the first one of the plurality of data entities, in response to input of the portion of the first one of the plurality of data entities to the address port of said RAM; wherein said RAM comprises an array of n RAMs, and wherein the each one of the plurality of data entities is segmented into n slices, each of the n slices being used as an address to a respective one of said array of n RAMs.

Claim 4

Dependent Claim 219 words

A content addressable memory comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address and containing one of a plurality of data entries; each of the data entries including predetermined match information for a portion of one of a plurality of data entities; each portion of each one of the plurality of data entities including said unique address of the data storage location containing the match information for the portion; said RAM having an address port for input of a portion of a first one of the plurality of data entities to the RAM as an address and the RAM operating to fetch the one of the plurality of data entries stored at said address; and said RAM having an output for output of match information corresponding to the portion of the first one of the plurality of data entities, in response to input of the portion of the first one of the plurality of data entities to the address port of said RAM; wherein said RAM comprises an array of n RAMs, and wherein the each one of the plurality of data entities is segmented into n slices, each of the n slices being used as an address to a respective one of said array of n RAMs.

Claim 5

Dependent Claim 202 words

A content addressable memory comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address; the unique address of each of said storage locations comprising a portion of one of x unique individual data entities; a data entry stored in each one of said data storage locations for providing match information for the portion of one of x unique individual data entities corresponding to each data storage location; each data entry comprising x bits of data, x being the number of unique individual data entities; each one of said x bits of each of said data entries comprising predetermined match information for a corresponding particular one of the x unique individual data entities; said RAM having an address port for input of a portion of a selected one of the x unique individual data entities to the RAM as an address; and said RAM having an x-bit output for output of match information corresponding to the portion of the selected one of the x unique individual data entities, in response to input of the portion of the selected one of the x unique individual data entities to the address port of said RAM.

Claim 6

Dependent Claim 202 words

A content addressable memory comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address; the unique address of each of said storage locations comprising a portion of one of x unique individual data entities; a data entry stored in each one of said data storage locations for providing match information for the portion of one of x unique individual data entities corresponding to each data storage location; each data entry comprising x bits of data, x being the number of unique individual data entities; each one of said x bits of each of said data entries comprising predetermined match information for a corresponding particular one of the x unique individual data entities; said RAM having an address port for input of a portion of a selected one of the x unique individual data entities to the RAM as an address; and said RAM having an x-bit output for output of match information corresponding to the portion of the selected one of the x unique individual data entities, in response to input of the portion of the selected one of the x unique individual data entities to the address port of said RAM.

Claim 7

Dependent Claim 216 words

An address recognition unit comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address and containing one of a plurality of data entries; each of the data entries being associated with a portion of one of a plurality of data entities and including predetermined match information for said portion of one of the plurality of data entities; each portion of one of the plurality of data entities including said unique address of the data storage location containing the associated one of the data entries; said RAM having an address port for input of a portion of a first one of the plurality of data entities to the RAM as an address and said RAM means operating to fetch the one of the plurality of data entries stored at said address; said RAM having an output for output of identification information corresponding to a portion of the first one of the plurality of data entities, in response to input of the portion of the first one of the plurality of data entities to the address port of said RAM and each portion of one of the plurality of data entities comprising unique identification information for a corresponding one of a plurality of components of a computer system.

Claim 8

Dependent Claim 216 words

An address recognition unit comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address and containing one of a plurality of data entries; each of the data entries being associated with a portion of one of a plurality of data entities and including predetermined match information for said portion of one of the plurality of data entities; each portion of one of the plurality of data entities including said unique address of the data storage location containing the associated one of the data entries; said RAM having an address port for input of a portion of a first one of the plurality of data entities to the RAM as an address and said RAM means operating to fetch the one of the plurality of data entries stored at said address; said RAM having an output for output of identification information corresponding to a portion of the first one of the plurality of data entities, in response to input of the portion of the first one of the plurality of data entities to the address port of said RAM and each portion of one of the plurality of data entities comprising unique identification information for a corresponding one of a plurality of components of a computer system.

Claim 9

Dependent Claim 174 words

An address recognition unit comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address; the unique address of each of said storage locations comprising a portion of one of x unique individual data entities; a data entry stored in each one of said data storage locations for providing identification information for the portion of one of x unique individual data entities corresponding to each data storage location; each data entry comprising x bits of data, x being the number of unique individual data entities; each one of said x bits of each of said data entries comprising predetermined identification information for a corresponding particular data entity; said RAM having an address port for input of the portion of a data entity to the RAM as an address; and said RAM having an x-bit output for output of match information corresponding to the portion of a data entity, in response to input of the portion of a data entity as an address to said RAM.

Claim 10

Dependent Claim 174 words

An address recognition unit comprising: a RAM including a plurality of data storage locations, each of said data storage locations having a unique address; the unique address of each of said storage locations comprising a portion of one of x unique individual data entities; a data entry stored in each one of said data storage locations for providing identification information for the portion of one of x unique individual data entities corresponding to each data storage location; each data entry comprising x bits of data, x being the number of unique individual data entities; each one of said x bits of each of said data entries comprising predetermined identification information for a corresponding particular data entity; said RAM having an address port for input of the portion of a data entity to the RAM as an address; and said RAM having an x-bit output for output of match information corresponding to the portion of a data entity, in response to input of the portion of a data entity as an address to said RAM.

Claim 11

Independent Claim 156 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; inputting a portion of a preselected one of the plurality of data entities as an address for one of the data storage locations to access the data entry stored in a corresponding one of the data storage locations, the data entry including match information corresponding to the portion of the preselected one of the plurality of data entities; segmenting each one of the plurality of data entities into n slices; arranging the RAM as an array of n RAMs; and inputting each of the n slices as an address to a respective one of the array of n RAMs.

Claim 12

Independent Claim 156 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; inputting a portion of a preselected one of the plurality of data entities as an address for one of the data storage locations to access the data entry stored in a corresponding one of the data storage locations, the data entry including match information corresponding to the portion of the preselected one of the plurality of data entities; segmenting each one of the plurality of data entities into n slices; arranging the RAM as an array of n RAMs; and inputting each of the n slices as an address to a respective one of the array of n RAMs.

Claim 13

Dependent Claim 55 words

The method of claim 6 further comprising the steps of: outputting match information from each one of the array of n RAMs to a respective input of an n-input AND gate; and outputting from the AND gate an output comprising a signal of ANDed match information from each one of the array of n RAMs.

Claim 14

Dependent Claim 194 words

The method of claim 6 further comprising the steps of: a) outputting to a logic device, from each one of the array of n RAMs a certain one of the data entries: 1) said certain one of the data entries including match information corresponding to the input of one of the n slices, 2) said certain one of the data entries including x bits, x being equal to a number of unique individual data entities for which match information is stored in a respective one of the data storage locations, 3) each one of the x-bits of the certain one of the data entries corresponding to a respective one of the x unique individual data entities; b) ANDing together, in the logic device, predetermined corresponding bits output from the n RAMs to generate ANDed together match information for each of the x unique individual data entities; and c) outputting, from the logic device, a mask signal comprising an x-bit mask signal, each bit of the x bit mask signal corresponding to one of the individual unique data entities, said x-bit mask signal indicating ANDed together match information for the x unique individual data entities.

Claim 15

Independent Claim 164 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; serially inputting to the RAM preselected slices of a portion of a preselected one of the plurality of data entities as addresses for the data storage locations to access the data entries stored in corresponding data storage locations, one slice per preselected time period, the data entries including match information corresponding to the preselected slices of the portion of the preselected one of the plurality of data entities; serially outputting match information from the RAM; and cumulatively ANDing together the serially output match information to generate a composite mask signal for the preselected slices of the portion of the preselected one of the plurality of data entities.

Claim 16

Independent Claim 164 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; serially inputting to the RAM preselected slices of a portion of a preselected one of the plurality of data entities as addresses for the data storage locations to access the data entries stored in corresponding data storage locations, one slice per preselected time period, the data entries including match information corresponding to the preselected slices of the portion of the preselected one of the plurality of data entities; serially outputting match information from the RAM; and cumulatively ANDing together the serially output match information to generate a composite mask signal for the preselected slices of the portion of the preselected one of the plurality of data entities.

Claim 17

Independent Claim 148 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: arranging the RAM as an array of n RAMs; storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; segmenting each one of the plurality of data entities into n slices; inputting each of the n slices as an address to a respective one of the array of n RAMs to access the data entry stored therein, the data entry including match information corresponding to the inputted slice of the data entity; outputting match information from the n RAMs; and ANDing together the output match information to generate a composite mask signal for the inputted n slices of the data entity.

Claim 18

Independent Claim 148 words

A method of operating a RAM to function as a content addressable memory comprising the steps of: arranging the RAM as an array of n RAMs; storing a data entry indicating match information for a portion of one of a plurality of data entities in each of a plurality of data storage locations of the RAM, each of the data storage locations having a unique address; segmenting each one of the plurality of data entities into n slices; inputting each of the n slices as an address to a respective one of the array of n RAMs to access the data entry stored therein, the data entry including match information corresponding to the inputted slice of the data entity; outputting match information from the n RAMs; and ANDing together the output match information to generate a composite mask signal for the inputted n slices of the data entity.

Claim 19

Dependent Claim 25 words

The method according to claim 10, wherein said n slices are inputted serially, and wherein said match information from said n RAMs is outputted serially.

Claim 20

Dependent Claim 23 words

The method according to claim 11, wherein said step of serially inputting said n slices comprises inputting one slice per preselected time period.

Claim 21

Dependent Claim 201 words

A content addressable memory comprising: a RAM having a plurality of data storage locations, each of said data storage locations having a unique address and containing one of a plurality of data entries; said RAM having an address port for inputting, as addresses, preselected slices of a portion of a preselected one of a plurality of data entities, wherein said RAM accesses the data entries stored in corresponding data storage locations, the data entries including match information corresponding to the preselected slices of a portion of the preselected one of the plurality of data entities; said RAM having an output port for outputting match information corresponding to the preselected slices of the portion of the preselected one of the plurality of data entities, in response to input of the preselected slices of the portion of the preselected one of the plurality of data entities; and said RAM having an AND operator for cumulatively ANDing together the output match information to generate a composite mask signal for the preselected slices of the portion of the preselected one of the plurality of data entities; wherein said address port inputs said preselected slices serially, and wherein said output port outputs said match information serially.

Claim 22

Dependent Claim 201 words

A content addressable memory comprising: a RAM having a plurality of data storage locations, each of said data storage locations having a unique address and containing one of a plurality of data entries; said RAM having an address port for inputting, as addresses, preselected slices of a portion of a preselected one of a plurality of data entities, wherein said RAM accesses the data entries stored in corresponding data storage locations, the data entries including match information corresponding to the preselected slices of a portion of the preselected one of the plurality of data entities; said RAM having an output port for outputting match information corresponding to the preselected slices of the portion of the preselected one of the plurality of data entities, in response to input of the preselected slices of the portion of the preselected one of the plurality of data entities; and said RAM having an AND operator for cumulatively ANDing together the output match information to generate a composite mask signal for the preselected slices of the portion of the preselected one of the plurality of data entities; wherein said address port inputs said preselected slices serially, and wherein said output port outputs said match information serially.

Claim 23

Dependent Claim 23 words

The content addressable memory according to claim 13, wherein said address port serially inputs said preselected slices, one slice per preselected time period.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-09-07	2002-03-09	2002-09-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-09-07	2006-03-09	2006-09-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-09-07	2010-03-09	2010-09-08	$7700.00	Window Closed / Lapsed

Apparatus and method for an improved content addressable memory using a random access memory to generate match information

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