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Patent US6166410A successfully refreshed from Google Patents.
US6166410A
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MONOS flash memory for multi-level logic and method thereof
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-10-05
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Granted: 2000-12-26
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Expires: 2018-10-05
Abstract
Abstract The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.
Inventors
- 👤 Ruei-Ling Lin
- 👤 Ching-Hsiang Hsu
- 👤 Mong-Song Liang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5671; H10B; H10B41/00; H10B41/30; H10B43/00; H10B43/30; H10B69/00; H10D30/69; H10D30/691; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/037
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
293 words
A multi-level logic flash memory cell comprising: a) a substrate having a floating gate channel area, a MONOS channel area, and a source area adjacent the floating gate channel area and a drain area adjacent the MONOS channel area; b) a tunnel oxide layer over said floating gate channel area and said MONOS channel area of said substrate; c) a poly floating gate electrode over said floating gate channel area; d) an ONO layer over said poly floating gate electrode and said tunnel oxide layer over said MONOS channel area; e) a control gate electrode over said ONO layer over said poly floating gate electrode and said MONOS channel area; f) shallow trench isolation regions in portions of said source and drain area in said substrate; g) a source region in said source area in said substrate adjacent to said floating gate channel area and under a portion of said poly floating gate electrode; h) a drain region in said drain area in said substrate adjacent to said MONOS channel area and under a portion of said ONO layer; said source and drain regions orientated in a first direction; i) an insulating layer over said control gate electrode over said MONOS channel area; j) a word line over said control gate electrode and said insulating layer; said word line oriented in a second direction perpendicular to said source and drain regions; k) said control gate electrode and said poly floating gate electrode forming a floating gate transistor over said floating gate channel area; and said ONO layer and said control gate electrode over said MONOS channel area forming a MONOS transistor over said MONOS channel area; and said multi-level logic flash memory cell comprised of said MONOS transistor and said floating gate transistor.
Claim 2
Dependent Claim
293 words
A multi-level logic flash memory cell comprising: a) a substrate having a floating gate channel area, a MONOS channel area, and a source area adjacent the floating gate channel area and a drain area adjacent the MONOS channel area; b) a tunnel oxide layer over said floating gate channel area and said MONOS channel area of said substrate; c) a poly floating gate electrode over said floating gate channel area; d) an ONO layer over said poly floating gate electrode and said tunnel oxide layer over said MONOS channel area; e) a control gate electrode over said ONO layer over said poly floating gate electrode and said MONOS channel area; f) shallow trench isolation regions in portions of said source and drain area in said substrate; g) a source region in said source area in said substrate adjacent to said floating gate channel area and under a portion of said poly floating gate electrode; h) a drain region in said drain area in said substrate adjacent to said MONOS channel area and under a portion of said ONO layer; said source and drain regions orientated in a first direction; i) an insulating layer over said control gate electrode over said MONOS channel area; j) a word line over said control gate electrode and said insulating layer; said word line oriented in a second direction perpendicular to said source and drain regions; k) said control gate electrode and said poly floating gate electrode forming a floating gate transistor over said floating gate channel area; and said ONO layer and said control gate electrode over said MONOS channel area forming a MONOS transistor over said MONOS channel area; and said multi-level logic flash memory cell comprised of said MONOS transistor and said floating gate transistor.
Claim 3
Dependent Claim
95 words
The multi-level logic flash memory cell of claim 1 wherein the program, erase and read voltages employed for memory operation of said multi-level logic flash memory cell device are as follows: ______________________________________
program
Floating
Gate program MONOS
Erase Read
______________________________________
Vg -4 V to -6 V
-4 V to -6 V 15 to 20 V
3 to 5 V
VD Floating 4 V to 6 V 0 V 1 to 2 V
VS 8 to 10 V Floating 0 V 0 V
______________________________________ whereby operation of said a multi-level logic flash memory cell is controlled.
Claim 4
Dependent Claim
66 words
The multi-level logic flash memory cell of claim 1 wherein VT employed for memory operation of said device are as follows: ______________________________________
Logic
Vt States Q1 Q2
______________________________________
[Vt0] VT0 erased charged charged
VT1 0 1 charged No Charge
[Vt2] VT2 1 0 No Charge Charge
[Vt3] VT3 1 1 NO Charge No Charge
______________________________________ whereby operation of said multi-level logic flash memory cell is controlled.
Claim 5
Dependent Claim
341 words
A multi-level logic flash memory cell comprising: a) a substrate having a floating gate channel area, a MONOS channel area, and a source area adjacent the floating gate channel area and a drain area adjacent the MONOS channel area; b) a tunnel oxide layer over said floating gate channel area and said MONOS channel area of said substrate; c) a poly floating gate electrode over said floating gate channel area; d) an ONO layer over said poly floating gate electrode and said tunnel oxide layer over said MONOS channel area; said ONO layer comprised of: a lower oxide layer, a nitride layer and a top oxide layer; e) a control gate electrode over said ONO layer over said poly floating gate electrode and said MONOS channel area; f) shallow trench isolation regions in portions of said source and drain area in said substrate; g) a source region in said source area said substrate adjacent to said floating gate channel area and under a portion of said poly floating gate electrode; h) a drain region in said drain area in said substrate adjacent to said MONOS channel area and under a portion of said ONO layer; said source and drain regions orientated in a first direction; i) an insulating layer over said control gate electrode over said MONOS channel area; j) a word line over said control gate electrode and said insulating layer; said word line oriented in a second direction perpendicular to said source and drain regions; k) said control gate electrode and said poly floating gate electrode forming a floating gate transistor over said floating gate channel area; and said ONO layer and said control gate over said MONOS channel area forming a MONOS transistor over said MONOS channel area; and said multi-level logic flash memory cell comprised of said MONOS transistor and said floating gate transistor: wherein the VT employed for memory operation of said multi-level logic flash cell is controlled by the Charge on said floating gate electrode and on said nitride layer over said MONOS channel area.
Claim 6
Dependent Claim
341 words
A multi-level logic flash memory cell comprising: a) a substrate having a floating gate channel area, a MONOS channel area, and a source area adjacent the floating gate channel area and a drain area adjacent the MONOS channel area; b) a tunnel oxide layer over said floating gate channel area and said MONOS channel area of said substrate; c) a poly floating gate electrode over said floating gate channel area; d) an ONO layer over said poly floating gate electrode and said tunnel oxide layer over said MONOS channel area; said ONO layer comprised of: a lower oxide layer, a nitride layer and a top oxide layer; e) a control gate electrode over said ONO layer over said poly floating gate electrode and said MONOS channel area; f) shallow trench isolation regions in portions of said source and drain area in said substrate; g) a source region in said source area said substrate adjacent to said floating gate channel area and under a portion of said poly floating gate electrode; h) a drain region in said drain area in said substrate adjacent to said MONOS channel area and under a portion of said ONO layer; said source and drain regions orientated in a first direction; i) an insulating layer over said control gate electrode over said MONOS channel area; j) a word line over said control gate electrode and said insulating layer; said word line oriented in a second direction perpendicular to said source and drain regions; k) said control gate electrode and said poly floating gate electrode forming a floating gate transistor over said floating gate channel area; and said ONO layer and said control gate over said MONOS channel area forming a MONOS transistor over said MONOS channel area; and said multi-level logic flash memory cell comprised of said MONOS transistor and said floating gate transistor: wherein the VT employed for memory operation of said multi-level logic flash cell is controlled by the Charge on said floating gate electrode and on said nitride layer over said MONOS channel area.
Claim 7
Dependent Claim
63 words
The multi-level logic flash memory cell of claim 4 wherein VT employed for memory operation of said device are as follows: ______________________________________
Logic
Vt States Q1 Q2
______________________________________
VT0 erased charged charged
VT1 0 1 charged No Charge
VT2 1 0 No Charge Charge
VT3 1 1 NO Charge No Charge
______________________________________ whereby operation of said multi-level logic flash memory cell is controlled.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |