Integration method for sidewall split gate monos transistor

Claim 1

A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising: providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said silicon nitride layer to the dimension of said word gate; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask; removing said block out mask; forming a insulator layer on said vertical sidewall; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is the channel for said device; ion implanting a N type dopant into said substrate to form a device region therein; removing said disposable sidewall spacer layer; removing the exposed gate silicon oxide layer; forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and device region; and forming said control gate sidewall spacer on said vertical sidewall and said composite layer.

Claim 2

A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising: providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said silicon nitride layer to the dimension of said word gate; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask; removing said block out mask; forming a insulator layer on said vertical sidewall; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is the channel for said device; ion implanting a N type dopant into said substrate to form a device region therein; removing said disposable sidewall spacer layer; removing the exposed gate silicon oxide layer; forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and device region; and forming said control gate sidewall spacer on said vertical sidewall and said composite layer.

Claim 12

A method of fabricating an electrically programmable read only memory device which is a word gate and a MONOS control gate on the sidewall of the word gate while also fabricating logic gates associated therewith in the same silicon substrate comprising: providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said silicon nitride layer to the dimension of said control/word gate in the memory cell area and to the dimension of the logic gate in the non-memory areas; forming a block out mask over said silicon nitride layer of the dimension of said word gate to allow only the side uncovered to which said control gate is to be formed; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask; removing said block out mask; forming a insulator layer on said vertical sidewall; simultaneously ion implanting boron and arsenic ions into the exposed substrate which results in doping the control gate channel region in the finished device and enhances ballistic injection; forming a disposable sidewall spacer layer on said vertical sidewall and over said insulator layer, wherein the width of said spacer layer is the channel for said device; ion implanting a N type dopant into said substrate to form a device region therein; removing said disposable sidewall spacer layer and the exposed said gate silicon oxide layer; forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and over said channel and said device region; forming said control gate sidewall spacer on said vertical sidewall and over said composite layer, and over the channel; forming a second block out mask over said silicon nitride layer to cover and protect said control/word gate and said control gate and to allow all other areas to be uncovered; removing the exposed said silicon oxide layer; vertically etching said polysilicon layer to said gate silicon oxide layer to form a vertical sidewall on the opposite side of said control gate in the memory device area and to form the logic device gates in the said logic areas while using said silicon nitride layer on said side uncovered as the mask; removing said second block out mask; and forming lightly doped drain devices by ion implantation and forming sidewall spaces using a sidewall spacer technique in said logic areas at said logic gates.

Claim 13

A method of fabricating an electrically programmable read only memory device which is a word gate and a MONOS control gate on the sidewall of the word gate while also fabricating logic gates associated therewith in the same silicon substrate comprising: providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said silicon nitride layer to the dimension of said control/word gate in the memory cell area and to the dimension of the logic gate in the non-memory areas; forming a block out mask over said silicon nitride layer of the dimension of said word gate to allow only the side uncovered to which said control gate is to be formed; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask; removing said block out mask; forming a insulator layer on said vertical sidewall; simultaneously ion implanting boron and arsenic ions into the exposed substrate which results in doping the control gate channel region in the finished device and enhances ballistic injection; forming a disposable sidewall spacer layer on said vertical sidewall and over said insulator layer, wherein the width of said spacer layer is the channel for said device; ion implanting a N type dopant into said substrate to form a device region therein; removing said disposable sidewall spacer layer and the exposed said gate silicon oxide layer; forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and over said channel and said device region; forming said control gate sidewall spacer on said vertical sidewall and over said composite layer, and over the channel; forming a second block out mask over said silicon nitride layer to cover and protect said control/word gate and said control gate and to allow all other areas to be uncovered; removing the exposed said silicon oxide layer; vertically etching said polysilicon layer to said gate silicon oxide layer to form a vertical sidewall on the opposite side of said control gate in the memory device area and to form the logic device gates in the said logic areas while using said silicon nitride layer on said side uncovered as the mask; removing said second block out mask; and forming lightly doped drain devices by ion implantation and forming sidewall spaces using a sidewall spacer technique in said logic areas at said logic gates.

Claim 20

A method of fabricating an electrically programmable read only memory device which is a word gate, and a MONOS control gate on the sidewall of the word gate, and an ultra short, non-planar channel comprising: providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said silicon nitride layer to the dimension of said word gate; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said control gate is to be formed; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask; removing said block out mask; forming a insulator layer on said vertical sidewall; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is the channel for said device; vertically etching into said substrate to form a step within said substrate; ion implanting a N type dopant into said step within said substrate to form a device region therein having said non-planar channel; removing said disposable sidewall spacer layer and the exposed said silicon oxide gate layer; forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and over said channel and said device region; and forming said floating gate sidewall spacer over said composite layer and said vertical sidewall and over said channel.

Claim 21

A method of fabricating an electrically programmable read only memory device which is a word gate, and a MONOS control gate on the sidewall of the word gate, and an ultra short, non-planar channel comprising: providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said silicon nitride layer to the dimension of said word gate; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said control gate is to be formed; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask; removing said block out mask; forming a insulator layer on said vertical sidewall; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is the channel for said device; vertically etching into said substrate to form a step within said substrate; ion implanting a N type dopant into said step within said substrate to form a device region therein having said non-planar channel; removing said disposable sidewall spacer layer and the exposed said silicon oxide gate layer; forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and over said channel and said device region; and forming said floating gate sidewall spacer over said composite layer and said vertical sidewall and over said channel.