← Back to Patent Explorer
US6184089B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating one-time programmable read only memory

Assignee: United Microelectronics Corp
•
Filing: 1999-01-27
•
Granted: 2001-02-06
•
Expires: 2019-01-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of fabricating a one-time programmable read only memory (OTP-ROM) with reduced size is disclosed. In accordance with the method of the present invention, a stacked structure is formed on a substrate. The stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate. The substrate beside the stacked structure is exposed by the stacked structure. An implanted region is formed in the exposed substrate beside the stacked structure. A spacer is formed on a sidewall of the stacked structure. A silicide layer is formed on the implanted region. A silicon nitride layer is formed to cover the second oxide layer, the spacer, and the silicide layer. A second polysilicon layer is formed to cover the silicon nitride layer. The second polysilicon layer is patterned to form a control gate. The first polysilicon layer is further patterned to form a floating gate.

Inventors

  • 👤 Kuang-Yeh Chang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 04:13
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 140 words
A method of fabricating a one-time programmable read only memory, comprising the steps of: forming a stacked structure on a substrate, wherein the stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate, and the substrate beside the stacked structure is exposed by the stacked structure; forming an implanted region in the exposed substrate beside the stacked structure; forming a spacer on a sidewall of the stacked structure; forming a silicide layer on the implanted region; forming a silicon nitride layer to directly cover the second oxide layer, the spacer, and the silicide layer, forming a second polysilicon layer to cover the silicon nitride layer; and patterning the second polysilicon layer to form a control gate and further patterning the first polysilicon layer to form a floating gate.
Claim 2
Independent Claim 140 words
A method of fabricating a one-time programmable read only memory, comprising the steps of: forming a stacked structure on a substrate, wherein the stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate, and the substrate beside the stacked structure is exposed by the stacked structure; forming an implanted region in the exposed substrate beside the stacked structure; forming a spacer on a sidewall of the stacked structure; forming a silicide layer on the implanted region; forming a silicon nitride layer to directly cover the second oxide layer, the spacer, and the silicide layer, forming a second polysilicon layer to cover the silicon nitride layer; and patterning the second polysilicon layer to form a control gate and further patterning the first polysilicon layer to form a floating gate.
Claim 3
Dependent Claim 15 words
The method of claim 1 , wherein the material of the spacer comprises silicon nitride.
Claim 4
Dependent Claim 15 words
The method of claim 1 , wherein the silicide layer comprises a titanium silicide layer.
Claim 5
Dependent Claim 18 words
The method of claim 1 , wherein the first polysilicon layer is formed by low-pressure chemical vapor deposition.
Claim 6
Dependent Claim 18 words
The method of claim 1 , wherein the second polysilicon layer is formed by low-pressure chemical vapor deposition.
Claim 7
Dependent Claim 60 words
The method of claim 1 , wherein the step of forming the silicide layer comprises: forming a metallic layer on the substrate exposed by the second oxide layer, the spacer, and the stacked structure; performing a thermal treatment to covert the metallic layer, which is in contact with the substrate, into the silicide layer; and removing the remaining metallic layer.
Claim 8
Dependent Claim 28 words
The method of claim 1 , wherein the step of patterning the second polysilicon layer and further patterning the first polysilicon layer comprises a photolithographic and etching process.
Claim 9
Dependent Claim 29 words
The method of claim 1 , wherein the further patterning of the first polysilicon layer comprises a self-aligned etching step with the second polysilicon layer serving as a mask.
Claim 10
Independent Claim 118 words
A method of fabricating a one-time programmable read only memory, comprising the steps of: forming a stacked structure on a substrate, wherein the stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate, and the substrate beside the stacked structure is exposed by the stacked structure; forming an implanted region in the exposed substrate beside the stacked structure; forming a spacer on a sidewall of the stacked structure; forming a silicide layer on the implanted region in the substrate; forming a silicon nitride layer to directly cover the second oxide layer, the spacer, and the silicide layer; forming a control gate on the silicon nitride layer.
Claim 11
Independent Claim 118 words
A method of fabricating a one-time programmable read only memory, comprising the steps of: forming a stacked structure on a substrate, wherein the stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate, and the substrate beside the stacked structure is exposed by the stacked structure; forming an implanted region in the exposed substrate beside the stacked structure; forming a spacer on a sidewall of the stacked structure; forming a silicide layer on the implanted region in the substrate; forming a silicon nitride layer to directly cover the second oxide layer, the spacer, and the silicide layer; forming a control gate on the silicon nitride layer.
Claim 12
Dependent Claim 41 words
The method of claim 9 , wherein the step of forming the silicide layer comprises: forming a metallic layer on the substrate; performing a thermal treatment to convert the metallic layer into the silicide layer; and removing the remaining metallic layer.
Claim 13
Dependent Claim 15 words
The method of claim 9 , wherein the material of the spacer comprises silicon nitride.
Claim 14
Dependent Claim 36 words
The method of claim 9 , wherein the step of forming the control gate comprises: forming a second polysilicon layer on the silicon nitride layer; and patterning the second polysilicon layer to form a control gate.
Claim 15
Dependent Claim 25 words
The method of claim 9 , further comprising patterning the first polysilicon layer to form a floating gate after the formation of the control gate.

References Cited (Backward Citations)

US5702965A Cited
US5705416A Cited
US5970371A Cited
US5879992A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-02-06 2004-08-07 2005-02-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-02-06 2008-08-07 2009-02-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-02-06 2012-08-07 2013-02-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag