Abstract A method is provided to fabricate a mask ROM device via a medium current implanter. For fabricating the mask ROM device, first, formation of an array of MOS transistors on a semiconductor substrate is achieved. Each of the MOS transistors includes a gate oxide film, a gate electrode, a source region and a drain region. After the formation of the array of transistors, a USG layer, a BPSG layer, metal electrodes and a passivation layer are sequentially formed. After an order from client, an etching back process is performed to remove selected portions of the passivation layer to form openings in accordance with a ROM code. The selected portions are located over the selected gate electrodes respectively. The portions of the BPSG layer within the openings are successively etched until the remained BPSG layer is in a predetermined thickness. Finally, ROM code ions are implanted into the substrate via a medium current implanter through the openings. The remained thickness of the etched-back BPSG layer within the openings is employed to form the code identification on the substrate. The method has the advantages of short turn around time and low fabrication cost.
A method for fabricating a ROM code pattern on an array of passivated MOS transistors on a semiconductor substrate, each of said passivated MOS transistors comprising a silicon glass overlayer and a passivation overlayer formed over said silicon glass overlayer, said method comprising the steps of: forming a photoresist layer over said array of passivated MOS transistors and removing selected portions of said photoresist layer to partially expose said passivation overlayer in accordance with a ROM code, the selected portions being located over a corresponding gate electrode; etching through the exposed portions of said passivation overlayer to form openings and expose portions of said silicon glass overlayer within the openings; etching the exposed portions of said silicon glass overlayer within the openings such that a remained thickness of said silicon glass overlayer above said corresponding gate electrode remains; wherein the remained thickness of said silicon glass overlayer within the openings allows ROM code ions to implant into said substrate.
Claim 2
Independent Claim
159 words
A method for fabricating a ROM code pattern on an array of passivated MOS transistors on a semiconductor substrate, each of said passivated MOS transistors comprising a silicon glass overlayer and a passivation overlayer formed over said silicon glass overlayer, said method comprising the steps of: forming a photoresist layer over said array of passivated MOS transistors and removing selected portions of said photoresist layer to partially expose said passivation overlayer in accordance with a ROM code, the selected portions being located over a corresponding gate electrode; etching through the exposed portions of said passivation overlayer to form openings and expose portions of said silicon glass overlayer within the openings; etching the exposed portions of said silicon glass overlayer within the openings such that a remained thickness of said silicon glass overlayer above said corresponding gate electrode remains; wherein the remained thickness of said silicon glass overlayer within the openings allows ROM code ions to implant into said substrate.
Claim 3
Dependent Claim
29 words
The method of claim 1 , wherein the ROM code ions are implanted via a current implanter operating at an energy level of about 100 keV to 360 keV.
Claim 4
Dependent Claim
50 words
The method of claim 2 , wherein the remained silicon glass overlayer comprises a USG (undoped silicon glass) layer with a thickness of about 1,500 Å to 2,000 Å and a BPSG (boron-phosphorous silicon glass) layer with a thickness of about 1,500 Å to 2,000 Å over said USG layer.