US6222246B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-chip having an on-chip decoupling capacitor
Assignee: Intel Corp
•
Filing: 1999-01-08
•
Granted: 2001-04-24
•
Expires: 2019-01-08
Abstract
Abstract A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.
Inventors
- 👤 Tak M. Mak
- 👤 Paul Winer
- 👤 Valluri R. Rao
- 👤 Richard H. Livengood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:38
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/023; H05K1/0231; H10W72/00; H10W90/00; H05K2201/00; H05K2201/10; H05K2201/10431; H05K2201/10507; H05K2201/1053; H05K2201/10545; H05K2201/10613; H05K2201/10621; H05K2201/10636; H05K2201/10734; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W72/942; H10W72/951; H10W72/952; H10W90/701; H10W90/721; H10W90/724; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
31 words
An integrated circuit device comprising: a semiconductor substrate; a plurality of electrical interconnects coupled to said circuit elements; and a first decoupling capacitor disposed on a backside of said semiconductor substrate.
Claim 2
Dependent Claim
31 words
An integrated circuit device comprising: a semiconductor substrate; a plurality of electrical interconnects coupled to said circuit elements; and a first decoupling capacitor disposed on a backside of said semiconductor substrate.
Claim 3
Dependent Claim
74 words
The integrated circuit device of claim 1 further comprising circuit elements, a first layer of conductive lines, and a second layer of conductive lines, said first layer of conductive lines and said second layer of conductive lines electrically connecting said circuit elements, said first layer of conductive lines located adjacent said circuit elements; at least one of said plurality of electrical interconnects coupled to at least one of said first layer of conductive lines.
Claim 4
Dependent Claim
45 words
The integrated circuit device of claim 1 further comprising circuit elements, power metal lines, and ground metal lines connected to said circuit elements, said first decoupling capacitor being coupled to at least one of said power lines and at least one of said ground lines.
Claim 5
Dependent Claim
40 words
The integrated circuit device of claim 1 wherein said first decoupling capacitor is located within a recess of said backside, said first decoupling capacitor and said semiconductor substrate each having a backside surface, with said backside surfaces being substantially co-planar.
Claim 6
Dependent Claim
71 words
The integrated circuit device of claim 1 attached to a package substrate having a top surface and an opposite bottom surface, said raised bump contacts of said integrated circuit being connected to lands on said top surface of said package substrate; wherein said package substrate has at least one first decoupling attached to said bottom surface, and is electric coupled to said lands on said top surface of said package substrate.
Claim 7
Dependent Claim
111 words
An integrated circuit device comprising: a semiconductor substrate; a first recess in said semiconductor substrate; circuit elements formed within said semiconductor substrate; conductive lines electrically coupling said circuit elements, said conductive lines comprising power and ground metal lines; a plurality of bump contacts disposed on said semiconductor substrate and coupled to said circuit elements; a plurality of electrical interconnects linked to said recess and coupled to said power and ground metal lines; and a first decoupling capacitor disposed in said first recess and electrically coupled to said plurality of electrical interconnects, said first decoupling capacitor and said semiconductor substrate each having a backside surface, with said backside surfaces being substantially co-planar.
Claim 8
Dependent Claim
111 words
An integrated circuit device comprising: a semiconductor substrate; a first recess in said semiconductor substrate; circuit elements formed within said semiconductor substrate; conductive lines electrically coupling said circuit elements, said conductive lines comprising power and ground metal lines; a plurality of bump contacts disposed on said semiconductor substrate and coupled to said circuit elements; a plurality of electrical interconnects linked to said recess and coupled to said power and ground metal lines; and a first decoupling capacitor disposed in said first recess and electrically coupled to said plurality of electrical interconnects, said first decoupling capacitor and said semiconductor substrate each having a backside surface, with said backside surfaces being substantially co-planar.
Claim 9
Dependent Claim
102 words
An assembly comprising: an integrated circuit device including a semiconductor substrate, circuit elements formed within said semiconductor substrate, a plurality of raised bump contacts disposed on said semiconductor substrate and coupled to said circuit elements, a plurality of electrical interconnects disposed on said semiconductor substrate and coupled to said circuit elements, and a first decoupling capacitor electrically coupled to said plurality of electrical interconnects; and a package substrate, said bump contacts of said integrated circuit being coupled to lands on said package substrate, said package substrate having at least one second decoupling capacitor, said second decoupling capacitor electrically coupled to said lands.
Claim 10
Dependent Claim
102 words
An assembly comprising: an integrated circuit device including a semiconductor substrate, circuit elements formed within said semiconductor substrate, a plurality of raised bump contacts disposed on said semiconductor substrate and coupled to said circuit elements, a plurality of electrical interconnects disposed on said semiconductor substrate and coupled to said circuit elements, and a first decoupling capacitor electrically coupled to said plurality of electrical interconnects; and a package substrate, said bump contacts of said integrated circuit being coupled to lands on said package substrate, said package substrate having at least one second decoupling capacitor, said second decoupling capacitor electrically coupled to said lands.
Claim 11
Dependent Claim
60 words
The assembly of claim 7 wherein said integrated circuit device further comprises a first layer of conductive lines and a second layer of conductive lines electrically coupled to said circuit elements, said first layer of conductive lines located adjacent said circuit elements, at least one of said electrical interconnects coupled to at least one of said first layer conductive lines.
Claim 12
Dependent Claim
47 words
The assembly of claim 7 wherein said integrated circuit device further comprises power metal lines and ground metal lines coupled to said circuit elements, said first decoupling capacitor coupled to at least one of said power metal lines and at least one of said ground metal lines.
Claim 13
Dependent Claim
44 words
The assembly of claim 7 wherein said integrated circuit device further comprises said first decoupling capacitor located within a recess in said semiconductor substrate, said first decoupling capacitor and said semiconductor substrate each having a backside surface, with said backside surfaces being substantially co-planar.
Claim 14
Dependent Claim
29 words
An integrated circuit device comprising: a semiconductor substrate; circuit elements formed within said semiconductor substrate; and a decoupling capacitor directly coupled to at least one of said circuit elements.
Claim 15
Dependent Claim
29 words
An integrated circuit device comprising: a semiconductor substrate; circuit elements formed within said semiconductor substrate; and a decoupling capacitor directly coupled to at least one of said circuit elements.
Claim 16
Dependent Claim
41 words
The integrated circuit device of claim 11 wherein said first decoupling capacitor is located within a recess in said semiconductor substrate, said first decoupling capacitor and said semiconductor substrate each having backside surfaces, with each said backside surface being substantially co-planar.
Claim 17
Dependent Claim
25 words
The integrated circuit device of claim 1 wherein said second decoupling capacitor is electrically coupled to at least one of said plurality of electrical interconnects.
Claim 18
Dependent Claim
37 words
The integrated circuit device of claim 13 further comprising power metal lines and ground metal lines connected to said circuit elements, said second decoupling capacitor electrically coupled to at least one of said plurality of electrical interconnects.
Claim 19
Dependent Claim
41 words
The integrated circuit device of claim 13 wherein said second decoupling capacitor is located within a recess in said semiconductor substrate, said second decoupling capacitor and said semiconductor substrate each having a backside surface, with said backside surfaces being substantially co-planar.
Claim 20
Dependent Claim
42 words
The integrated circuit device of claim 6 further comprising a second decoupling capacitor disposed in a second recess in said second surface, said second decoupling capacitor and said semiconductor substrate each having a backside surface, with said backside surfaces being substantially co-planar.
Claim 21
Dependent Claim
22 words
The integrated circuit device of claim 4 further comprising a heat dissipating device attached to at least one of said backside surfaces.
References Cited (Backward Citations)
US4811082A
Cited
US5239198A
Cited
US6027980A
Cited
US5702984A
Cited
US5772451A
Cited
US5974662A
Cited
JPH07184178A
Cited
US5870289A
Cited
US5608261A
Cited
US5764070A
Cited
US5528209A
Cited
US5600257A
Cited
US5926359A
Cited
US5629383A
Cited
US5811868A
Cited
US5903050A
Cited
US5977640A
Cited
US6075712A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-04-23 | 2004-10-23 | 2005-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-04-23 | 2008-10-23 | 2009-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-04-23 | 2012-10-23 | 2013-04-24 | $7700.00 | Window Closed / Lapsed |