← Back to Patent Explorer
US6236059B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Memory cell incorporating a chalcogenide element and method of making same

Assignee: Round Rock Research LLC
•
Filing: 1997-04-30
•
Granted: 2001-05-22
•
Expires: 2017-04-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

Inventors

  • 👤 Graham R. Wolstenholme
  • 👤 Fernando Gonzalez
  • 👤 Russell C. Zahorik

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 10:51
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10B; H10B63/00; H10B63/10; H10B63/20; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 63 words
A memory cell, comprising: a semiconductor substrate having a conducting element disposed therein; and a chalcogenide element provided by: forming a first insulating layer on said semiconductor substrate; forming a pore in said first insulating layer extending to said conducting element; forming a layer of chalcogenide material only in said pore; and forming a first conducting layer in contact with said chalcogenide material.
Claim 2
Dependent Claim 63 words
A memory cell, comprising: a semiconductor substrate having a conducting element disposed therein; and a chalcogenide element provided by: forming a first insulating layer on said semiconductor substrate; forming a pore in said first insulating layer extending to said conducting element; forming a layer of chalcogenide material only in said pore; and forming a first conducting layer in contact with said chalcogenide material.
Claim 3
Dependent Claim 70 words
The memory cell of claim 1 , wherein said step of forming said layer of chalcogenide material in said pore comprises: forming a layer of chalcogenide material on said first insulating layer, wherein a portion of said layer of chalcogenide material is disposed in said pore and contacts said conducting element; and selectively removing said portion of said layer of chalcogenide material that is disposed superadjacent said first insulating layer.
Claim 4
Dependent Claim 37 words
The memory cell of claim 2 , wherein said step of selectively removing said portion of said layer of chalcogenide material comprises planarizing said layer of chalcogenide material to said first insulating layer by chemical mechanical planarization.
Claim 5
Dependent Claim 25 words
The memory cell of claim 1 , wherein a layer of titanium silicide is provided between said layer of chalcogenide material and said conductive element.
Claim 6
Dependent Claim 24 words
The memory cell of claim 1 , wherein a layer of carbon is provided between said layer of chalcogenide material and said conductive element.
Claim 7
Dependent Claim 24 words
The memory cell of claim 5 , wherein a layer of titanium silicide is provided between said layer of carbon and said conductive element.
Claim 8
Dependent Claim 25 words
The memory cell of claim 1 , wherein a second conducting layer is provided between said layer of chalcogenide material and said first conducting layer.

References Cited (Backward Citations)

US5705430A Cited
US5831276A Cited
US5841150A Cited
US5789277A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-05-21 2004-11-20 2005-05-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-05-21 2008-11-20 2009-05-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-05-21 2012-11-20 2013-05-22 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag