Three-dimensional container diode for use with multi-state material in a non-volatile memory cell

Claim 2

A multi-state material-based memory cell disposed on a substrate, said memory cell having a first node and a second node, said cell comprising: a container having a side extending from a top surface of said substrate downwardly into said substrate; a diode formed in a region of said substrate proximate to said container side, said diode being disposed between said first node and said side of said container; and a multi-state material memory element electrically coupled between said diode and said second node of said memory cell.

Claim 3

The memory cell of claim 1, wherein said multi-state material comprises a chalcogenide.

Claim 4

The memory cell of claim 2, wherein said first node is disposed in said substrate.

Claim 5

The memory cell of claim 2, wherein said diode comprises a first diode layer formed in said substrate in a region proximate to at least a portion of said container, and a second diode layer disposed inside said first diode layer.

Claim 6

The memory cell of claim 4, wherein said first diode layer is an implanted layer of N- type silicon.

Claim 7

The memory cell of claim 5, wherein said second diode layer is a layer of P+ type silicon formed by angled ion implantation of said first layer.

Claim 8

The memory cell of claim 2, comprising a diode contact disposed in electrical contact between said diode and said multi-state material memory element.

Claim 9

The memory cell of claim 2, wherein said memory element comprises a chalcogenide layer and an insulative layer, said insulative layer contouring said chalcogenide layer so as to define a chalcogenide active area at a center of said memory cell where said chalcogenide layer is in electrical communication with said diode.

Claim 10

The memory cell of claim 2, wherein said memory element comprises a chalcogenide layer and a cap layer, said cap layer defining a contact opening at a center of said memory cell where said second node is in electrical communication with said chalcogenide layer.

Claim 11

A memory matrix comprising a plurality of memory cells according to claim 1, said memory cells being disposed between a plurality of first address lines and second address lines, and wherein: (i) said first node is electrically connected to one of said first address lines and said second node is electrically connected to one of said second address lines; and (ii) said diode is electrically coupled between said memory element and said first node.

Claim 12

The memory matrix of claim 10, wherein each said container is substantially filled with a filler layer effective to electrically isolate opposing sides of said container, and wherein a memory cell is constructed proximate to each of said opposing sides of said container.

Claim 13

The memory matrix of claim 11, wherein said filler layer is an oxide layer.

Claim 14

The memory matrix of claim 10, wherein said first address line is a digitline and said second address line is a wordline.

Claim 15

The memory matrix of claim 10, wherein said first address line and said first node of each said memory cell are disposed in a surface of said substrate, and wherein each said first node is a part of one of said first address lines.

Claim 16

The memory matrix of claim 14, wherein said first node is electrically coupled to said diode.

Claim 17

The memory matrix of claim 15, wherein a strapping layer is disposed in electrical contact with each of said first address lines.

Claim 18

The memory matrix of claim 16, wherein said first address line is tungsten and said strapping layer is a TiSi 2 layer.

Claim 19

A pair of first and second multi-state material-based memory cells disposed on a substrate, each of said memory cells having a first node and a second node, said pair of cells comprising: a container having two opposing sides extending from a top surface of said substrate downwardly into said substrate; first and second diodes disposed proximate to said two opposing sides of said container; a first multi-state material memory element electrically coupled between said first diode and said second node of said first memory cell; and a second multi-state material memory element electrically coupled between said second diode and said second node of said second memory cell.

Claim 20

A pair of first and second multi-state material-based memory cells disposed on a substrate, each of said memory cells having a first node and a second node, said pair of cells comprising: a container having two opposing sides extending from a top surface of said substrate downwardly into said substrate; first and second diodes disposed proximate to said two opposing sides of said container; a first multi-state material memory element electrically coupled between said first diode and said second node of said first memory cell; and a second multi-state material memory element electrically coupled between said second diode and said second node of said second memory cell.

Claim 21

The memory cell pair of claim 18, wherein said multi-state material comprises a chalcogenide.

Claim 22

The memory cell pair of claim 19, wherein said first node of said first memory cell is electrically coupled to said first diode, and wherein said first node of said second memory cell is electrically coupled to said second diode.

Claim 23

The memory cell pair of claim 20, wherein said first multi-state memory element is disposed proximate to said first diode and said first node of said first memory cell; and wherein said second multi-state memory element is disposed proximate to said second diode and said first node of said second memory cell.

Claim 24

The memory cell pair of claim 21, wherein said first and second diodes are electrically isolated from each other.

Claim 25

The memory cell pair of claim 22, wherein each of said first and second diodes comprises a respective first diode layer disposed in at least a portion of a region of said substrate proximate to said two opposing sides of said container, and a second diode layer disposed inside said first diode layer.

Claim 26

The memory cell pair of claim 23, wherein said first diode layer of each of said first and second diodes is a layer of N type silicon.

Claim 27

The memory cell pair of claim 24, wherein said second diode layer of each of said first and second diodes is a layer of P type silicon.

Claim 28

The memory cell pair of claim 24, wherein said second diode layer of each of said first and second diodes is a layer of metal, said first diode layer and second diode layer comprising a Schottky diode.

Claim 29

The memory cell pair of claim 22, wherein said substrate is p-type silicon.

Claim 30

A memory matrix comprising a plurality of memory cell pairs according to claim 19.

Claim 31

A chalcogenide-based memory matrix formed on a structure having an oxide layer disposed above a p-type silicon substrate, said matrix comprising: a plurality of memory cells disposed between a plurality of TiSi 2 strapped N+ type silicon digitlines disposed along an upper surface of said substrate, and a plurality of aluminum wordlines, each said memory cell comprising: (i) a first node and a second node, said first node being disposed along an upper surface of said substrate and being electrically connected to one of said digitlines and said second node being electrically connected to one of said wordlines; (ii) a multi-state memory element electrically coupled to said second node, said memory element comprising a chalcogenide layer disposed between a lower electrode layer and an upper electrode layer, wherein each of said electrode layers comprises a layer of metal and a layer of carbon, said carbon layer disposed between the metal layer and the chalcogenide layer; (iii) a diode disposed in a TiSi 2 -lined container extending from an upper surface of said oxide layer downwardly into a hole formed in said oxide layer, said diode being electrically coupled between said memory element and said first node and comprising first and second diode layers, said first diode layer being of N- type silicon disposed proximate to at least a portion of an inner surface of said TiSi 2 -lined container, and said second diode layer being of P+ type silicon disposed concentrically inside said first diode layer, an outer surface of said first diode layer being in electrical communication with said first node; (iv) a TiW contact layer disposed between said memory element and said wordline; (v) a TiW plug layer disposed between said second diode layer and said memory element; (vi) a nitride insulative layer disposed between said plug layer and said memory element, said insulative layer contouring said chalcogenide layer so as to define a chalcogenide active area at a center of said memory cell where said chalcogenide layer is in electrical communication with said plug layer; and (vii) a nitride cap layer disposed between said memory element and said contact layer, said cap layer contouring said contact layer so as to define a contact opening at a center of said memory cell where said contact layer is in electrical communication with said chalcogenide layer.

Claim 32

A chalcogenide-based memory matrix formed on a structure having an oxide layer disposed above a p-type silicon substrate, said matrix comprising: a plurality of memory cells disposed between a plurality of TiSi 2 strapped N+ type silicon digitlines disposed along an upper surface of said substrate, and a plurality of aluminum wordlines, each said memory cell comprising: (i) a first node and a second node, said first node being disposed along an upper surface of said substrate and being electrically connected to one of said digitlines and said second node being electrically connected to one of said wordlines; (ii) a multi-state memory element electrically coupled to said second node, said memory element comprising a chalcogenide layer disposed between a lower electrode layer and an upper electrode layer, wherein each of said electrode layers comprises a layer of metal and a layer of carbon, said carbon layer disposed between the metal layer and the chalcogenide layer; (iii) a diode disposed in a TiSi 2 -lined container extending from an upper surface of said oxide layer downwardly into a hole formed in said oxide layer, said diode being electrically coupled between said memory element and said first node and comprising first and second diode layers, said first diode layer being of N- type silicon disposed proximate to at least a portion of an inner surface of said TiSi 2 -lined container, and said second diode layer being of P+ type silicon disposed concentrically inside said first diode layer, an outer surface of said first diode layer being in electrical communication with said first node; (iv) a TiW contact layer disposed between said memory element and said wordline; (v) a TiW plug layer disposed between said second diode layer and said memory element; (vi) a nitride insulative layer disposed between said plug layer and said memory element, said insulative layer contouring said chalcogenide layer so as to define a chalcogenide active area at a center of said memory cell where said chalcogenide layer is in electrical communication with said plug layer; and (vii) a nitride cap layer disposed between said memory element and said contact layer, said cap layer contouring said contact layer so as to define a contact opening at a center of said memory cell where said contact layer is in electrical communication with said chalcogenide layer.

Claim 33

A chalcogenide based memory matrix formed on a p-type silicon substrate, said matrix comprising: a plurality of memory cell pairs disposed between a plurality of TiSi 2 strapped buried tungsten digitlines disposed in a surface of said substrate and a plurality of aluminum wordlines, each said memory pair comprising: (i) a pair of first nodes and a pair of second nodes, each said first nodes being disposed in a surface of said substrate and being electrically connected to one of said digitlines, and each said second nodes being electrically connected to one of said wordlines; (ii) a pair of multi-state memory elements, each of said multi-state memory elements being electrically coupled to one of said second nodes, and each of said memory elements comprising a chalcogenide layer disposed above one of said digitlines and between a lower electrode layer and an upper electrode layer, wherein each of said electrode layers comprises a layer of metal and a layer of carbon, said carbon layer disposed between the metal layer and the chalcogenide layer; (iii) a container having four sides disposed below said pair of memory elements and extending from a top surface of said substrate downwardly into a trench formed in said substrate, two opposing sides of said diode being defined by a trench in said substrate, and two opposing sides defined by an oxide layer substantially filling said trench; (iv) a pair of diodes, each said diode being disposed below and proximate to one of said memory elements in said substrate in a region proximate to one of said two opposing sides of said container defined by said trench, at least a portion of said side of said container being lined with TiSi 2 , each said diode being electrically coupled between one of said respective sides of said container and one of said first nodes; and wherein each said diode comprises: a first diode layer of N-type silicon formed by angular ion implantation of at least a portion of a region of said substrate proximate to one of said opposing sides of said container and a second diode layer of P+ type silicon disposed inside said first diode layer and formed by angular ion implantation of an inner surface of said first diode layer, said inner surface of said first diode layer facing inwardly toward a center of said container, and said first diode layer having an outer surface facing outwardly away from said center of said container and being in electrical communication with said first node; (v) a filler layer disposed inside said diode container, said filler layer being effective to isolate opposite sides of said container; (vi) a TiSi 2 -strapped tungsten diode contact disposed in electrical contact between each of said second diode layers and each of said lower electrode layers; (vii) a nitride insulative layer disposed between each of said lower electrode layers and each said memory element, said insulative layer contouring said chalcogenide layer so as to define a chalcogenide active area at a center of said memory cell where said chalcogenide layer is in electrical communication with said diode; and (viii) a nitride cap layer disposed between each of said memory elements and each of said upper electrode layers, said cap layer contouring said upper electrode layer so as to define a contact opening at a center of said memory cell where said upper electrode layer is in electrical communication with said chalcogenide layer.

Claim 34

A chalcogenide based memory matrix formed on a p-type silicon substrate, said matrix comprising: a plurality of memory cell pairs disposed between a plurality of TiSi 2 strapped buried tungsten digitlines disposed in a surface of said substrate and a plurality of aluminum wordlines, each said memory pair comprising: (i) a pair of first nodes and a pair of second nodes, each said first nodes being disposed in a surface of said substrate and being electrically connected to one of said digitlines, and each said second nodes being electrically connected to one of said wordlines; (ii) a pair of multi-state memory elements, each of said multi-state memory elements being electrically coupled to one of said second nodes, and each of said memory elements comprising a chalcogenide layer disposed above one of said digitlines and between a lower electrode layer and an upper electrode layer, wherein each of said electrode layers comprises a layer of metal and a layer of carbon, said carbon layer disposed between the metal layer and the chalcogenide layer; (iii) a container having four sides disposed below said pair of memory elements and extending from a top surface of said substrate downwardly into a trench formed in said substrate, two opposing sides of said diode being defined by a trench in said substrate, and two opposing sides defined by an oxide layer substantially filling said trench; (iv) a pair of diodes, each said diode being disposed below and proximate to one of said memory elements in said substrate in a region proximate to one of said two opposing sides of said container defined by said trench, at least a portion of said side of said container being lined with TiSi 2 , each said diode being electrically coupled between one of said respective sides of said container and one of said first nodes; and wherein each said diode comprises: a first diode layer of N-type silicon formed by angular ion implantation of at least a portion of a region of said substrate proximate to one of said opposing sides of said container and a second diode layer of P+ type silicon disposed inside said first diode layer and formed by angular ion implantation of an inner surface of said first diode layer, said inner surface of said first diode layer facing inwardly toward a center of said container, and said first diode layer having an outer surface facing outwardly away from said center of said container and being in electrical communication with said first node; (v) a filler layer disposed inside said diode container, said filler layer being effective to isolate opposite sides of said container; (vi) a TiSi 2 -strapped tungsten diode contact disposed in electrical contact between each of said second diode layers and each of said lower electrode layers; (vii) a nitride insulative layer disposed between each of said lower electrode layers and each said memory element, said insulative layer contouring said chalcogenide layer so as to define a chalcogenide active area at a center of said memory cell where said chalcogenide layer is in electrical communication with said diode; and (viii) a nitride cap layer disposed between each of said memory elements and each of said upper electrode layers, said cap layer contouring said upper electrode layer so as to define a contact opening at a center of said memory cell where said upper electrode layer is in electrical communication with said chalcogenide layer.