Method and apparatus for assembling array and datapath macros

Claim 2

A computer implemented method for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits comprising the steps of: (a) receiving initial user selections for a hierarchical macro to be created; said initial user selections including a command list of multiple leaf cell build commands; responsive to said received initial user selections, automatically performing the steps of: (b) initializing X and Y placer pointers; (c) obtaining a next build command from the command list and identifying a command type; (d) identifying a next leaf cell build command in a leaf cell group; (e) identifying a user selected schematic or physical view, and reading a corresponding leaf cell view for the user selected schematic or physical view; said leaf cell view represented by a symbol; (f) obtaining X and Y sizes for the leaf cell view; (g) orienting and placing the leaf cell; including the steps of providing connections to adjacent leaf cells by abutting leaf cells together; (h) calculating next X and Y placer pointers; and (i) repeating steps (d)-(h) until a last leaf cell build command in the leaf cell group is found; (j) returning to step (c) for obtaining a next build command from the command list and identifying a command type; (k) for the user selected schematic view, obtaining each unconnected pin from all symbols along the perimeter of the placed leaf cells, and connecting said obtained pins to schematic pins of same name and type; (l) condensing said schematic pins by removing bussing from single bit busses and combining bussed single pins into multiple bit bus pins; and (m) creating a symbol view; and (n) moving said combined bus pins to different sides and adjusting pin spacing of said moved pins responsive to received user selections.

Claim 3

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the steps of adding global power and ground busing responsive to identified user selections for a user selected physical view.

Claim 4

A computer implemented method for assembling array and datapath macros as recited in claim 2 further comprising the step of numbering of bits in bussed pins and adjusting pin types for a user selected physical view responsive to identified user selections.

Claim 5

A computer implemented method for assembling array and datapath macros as recited in claim 2 further comprising the steps of numbering of bits in bussed pins and adjusting pin types for a user selected schematic view responsive to identified user selections.

Claim 6

A computer implemented method for assembling array and datapath macros as recited in claim 2 further comprising the step of adding text to pins for said user selected physical view.

Claim 7

A computer implemented method for assembling array and datapath macros as recited in claim 2 further comprising the step of adding a boundary box on a level GROWBOX for said user selected physical view.

Claim 8

A computer implemented method for assembling array and datapath macros as recited in claim 6 further comprising the step of modifying a size of said boundary box for said user selected physical view.

Claim 9

A computer implemented method for assembling array and datapath macros as recited in claim 2 further comprising the step of for the user selected physical view, moving said schematic pin locations to a predefined grid.

Claim 10

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the steps of (o) creating a bounding box for the created symbol and adjusting size of the bounding box responsive to received users selections.

Claim 11

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the step (p) adding one of an instance label, a cell name label or a library name label.

Claim 12

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the step of propagating connections from a periphery of an array of placed leaf cells to a next hierarchical level.

Claim 13

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the step of pin mapping for renaming pins and for changing types of pins.

Claim 14

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the steps of identifying user selection for override of listed pins, and making said listed pins global.

Claim 15

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the step of adding notes to a created symbol view.

Claim 16

A computer implemented method for assembling array and datapath macros as recited in claim 14 further comprising the step of sorting pins on said symbol view by location in the schematic view or alphanumerically.

Claim 17

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the step of identifying a user selection for separate bus of listed pins, said listed pins being bussed and not being shorted.

Claim 18

A computer implemented method for assembling array and datapath macros as recited in claim 1 further comprising the step of identifying user selected directives to override default values.

Claim 19

Apparatus for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits comprising: means for receiving initial user selections for a hierarchical macro to be created; said initial user selections including a command list of multiple leaf cell build commands; means, responsive to said initial user selections receiving means, for automatically assembling array and datapath macros including: means for initializing X and Y placer pointers; means for obtaining a next build command from the command list and identifying a command type; means, responsive to identifying a next leaf cell build command in a leaf cell group, for identifying a user selected schematic or physical view, and for reading a corresponding leaf cell view for the user selected schematic or physical view; said leaf cell view represented by a symbol; means, responsive to said read leaf cell view, for obtaining X and Y sizes for said leaf cell view; means, responsive to said obtained X and Y sizes, for orienting and for placing said leaf cell, and for providing connections to adjacent leaf cells by abutting leaf cells together; means, responsive to said placed leaf cell, for calculating next X and Y placer pointers; means for sequentially processing said leaf cells until a last leaf cell build command in the leaf cell group is found; and means, responsive to said last leaf cell build command for obtaining the next build command from the command list and for identifying the command type; for the user selected schematic view, means for obtaining each unconnected pin from all symbols along the perimeter of the placed leaf cells, and for connecting said obtained pins to schematic pins of same name and type; means for condensing said schematic pins by removing bussing from single bit busses and combining bussed single pins into multiple bit bus pins; and means for creating a symbol view; and for moving said combined bus pins to different sides and for adjusting pin spacing of said moved pins responsive to received user selections.

Claim 20

Apparatus for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits comprising: means for receiving initial user selections for a hierarchical macro to be created; said initial user selections including a command list of multiple leaf cell build commands; means, responsive to said initial user selections receiving means, for automatically assembling array and datapath macros including: means for initializing X and Y placer pointers; means for obtaining a next build command from the command list and identifying a command type; means, responsive to identifying a next leaf cell build command in a leaf cell group, for identifying a user selected schematic or physical view, and for reading a corresponding leaf cell view for the user selected schematic or physical view; said leaf cell view represented by a symbol; means, responsive to said read leaf cell view, for obtaining X and Y sizes for said leaf cell view; means, responsive to said obtained X and Y sizes, for orienting and for placing said leaf cell, and for providing connections to adjacent leaf cells by abutting leaf cells together; means, responsive to said placed leaf cell, for calculating next X and Y placer pointers; means for sequentially processing said leaf cells until a last leaf cell build command in the leaf cell group is found; and means, responsive to said last leaf cell build command for obtaining the next build command from the command list and for identifying the command type; for the user selected schematic view, means for obtaining each unconnected pin from all symbols along the perimeter of the placed leaf cells, and for connecting said obtained pins to schematic pins of same name and type; means for condensing said schematic pins by removing bussing from single bit busses and combining bussed single pins into multiple bit bus pins; and means for creating a symbol view; and for moving said combined bus pins to different sides and for adjusting pin spacing of said moved pins responsive to received user selections.

Claim 21

A computer program product for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits, said computer program product including a plurality of computer executable instructions stored on a computer readable medium, wherein said instructions, when executed by said computer, cause the computer to perform the steps of: (a) receiving initial user selections for a hierarchical macro to be created; said initial user selections including a command list of multiple leaf cell build commands; responsive to said received initial user selections, automatically performing the steps of: (b) initializing X and Y placer pointers; (c) obtaining a next build command from the command list and identifying a command type; (d) identifying a next leaf cell build command in a leaf cell group; (e) identifying a user selected schematic or physical view, and reading a corresponding leaf cell view for the user selected schematic or physical view; said leaf cell view represented by a symbol; (f) obtaining X and Y sizes for the leaf cell view; (g) orienting and placing the leaf cell and providing connections to adjacent leaf cells by abutting leaf cells together; (h) calculating next X and Y placer pointers; and (i) repeating steps (d)-(h) until a last leaf cell build command in the leaf cell group is found; (j) returning to step (c) for obtaining a next build command from the command list and identifying a command type; (k) for the user selected schematic view, obtaining each unconnected pin from all symbols along the perimeter of the placed leaf cells, and connecting said obtained pins to schematic pins of same name and type; (l) condensing said schematic pins by removing bussing from single bit busses and combining bussed single pins into multiple bit bus pins; and (m) creating a symbol view; and (n) moving said combined pins to different sides and adjusting pin spacing of said moved pins responsive to received user selections.

Claim 22

A computer program product for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits, said computer program product including a plurality of computer executable instructions stored on a computer readable medium, wherein said instructions, when executed by said computer, cause the computer to perform the steps of: (a) receiving initial user selections for a hierarchical macro to be created; said initial user selections including a command list of multiple leaf cell build commands; responsive to said received initial user selections, automatically performing the steps of: (b) initializing X and Y placer pointers; (c) obtaining a next build command from the command list and identifying a command type; (d) identifying a next leaf cell build command in a leaf cell group; (e) identifying a user selected schematic or physical view, and reading a corresponding leaf cell view for the user selected schematic or physical view; said leaf cell view represented by a symbol; (f) obtaining X and Y sizes for the leaf cell view; (g) orienting and placing the leaf cell and providing connections to adjacent leaf cells by abutting leaf cells together; (h) calculating next X and Y placer pointers; and (i) repeating steps (d)-(h) until a last leaf cell build command in the leaf cell group is found; (j) returning to step (c) for obtaining a next build command from the command list and identifying a command type; (k) for the user selected schematic view, obtaining each unconnected pin from all symbols along the perimeter of the placed leaf cells, and connecting said obtained pins to schematic pins of same name and type; (l) condensing said schematic pins by removing bussing from single bit busses and combining bussed single pins into multiple bit bus pins; and (m) creating a symbol view; and (n) moving said combined pins to different sides and adjusting pin spacing of said moved pins responsive to received user selections.

Claim 23

A computer program product for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits as recited in claim 19 wherein said instructions, when executed by said computer, further cause the computer to perform the steps of propagating connections from a periphery of an array of placed leaf cells to a next hierarchical level.

Claim 24

A computer program product for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits as recited in claim 19 wherein said instructions, when executed by said computer, further cause the computer to perform the steps of identifying user selected directives to override default values.