Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Claim 1

The method of making a nonvolatile memory cell comprising: providing a pair of source and drain regions formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; providing a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; providing a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; forming a first gate electrode on said first gate insulator; forming a second gate electrode on said second gate insulator; wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers and wherein a carrier infected from said source region to said second channel forming region is injected in said second gate insulator by getting over a potential barrier between said first layer of said second gate insulator and said second channel forming region; forming a first potential feeding means which feeds to said drain region the first potential to supply to said carrier such energy that said carrier may get over said potential barrier formed between said second channel forming region and said first layer of said second gate insulator; and forming a second potential feeding means which feeds to said second gate electrode the potential to form an auxiliary electric field capable of having said carrier which has overcome said potential barrier reached said second layer of said second gate insulator.

Claim 2

The method of making a nonvolatile memory cell comprising: providing a pair of source and drain regions formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; providing a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; providing a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; forming a first gate electrode on said first gate insulator; forming a second gate electrode on said second gate insulator; wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers and wherein a carrier infected from said source region to said second channel forming region is injected in said second gate insulator by getting over a potential barrier between said first layer of said second gate insulator and said second channel forming region; forming a first potential feeding means which feeds to said drain region the first potential to supply to said carrier such energy that said carrier may get over said potential barrier formed between said second channel forming region and said first layer of said second gate insulator; and forming a second potential feeding means which feeds to said second gate electrode the potential to form an auxiliary electric field capable of having said carrier which has overcome said potential barrier reached said second layer of said second gate insulator.

Claim 3

The method of claims 1 wherein an insulating material is formed at least on end surfaces of one gate electrode out of said first and second gate electrodes.

Claim 11

The method of making a nonvolatile memory cell comprising: forming a pair of source/drain regions in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate, said channel forming semiconductor regions comprising a first channel forming semiconductor region, a second channel forming semiconductor region at one side and a second channel forming semiconductor region at the other side; forming a second gate insulator at one side on a surface of said second channel forming semiconductor region at one side adjacent to a source/drain region at one side out of said channel forming semiconductor regions; forming a second gate insulator at the other side on a surface of said second channel forming semiconductor region at the other side adjacent to the other source/drain region out of said channel forming regions; forming a first gate insulator on a surface of the first channel forming semiconductor region between each of said second channel forming regions; forming a second gate electrode at one side on said second gate insulator at one side; forming a second gate electrode at the other side on said second gate insulator at the other side; forming a first gate electrode on said first gate insulator, wherein said second insulators at one and the other sides are provided with carrier charge trapping means; and forming an insulating material at least on end surfaces of one gate electrode out of said first and second gate electrodes wherein said insulating material is of a side-wall insulating material left by anisotropically etching said insulating layer material which is uniformly formed on the main surface of said substrate.

Claim 12

The method of making a nonvolatile memory cell comprising: forming a pair of source/drain regions in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate, said channel forming semiconductor regions comprising a first channel forming semiconductor region, a second channel forming semiconductor region at one side and a second channel forming semiconductor region at the other side; forming a second gate insulator at one side on a surface of said second channel forming semiconductor region at one side adjacent to a source/drain region at one side out of said channel forming semiconductor regions; forming a second gate insulator at the other side on a surface of said second channel forming semiconductor region at the other side adjacent to the other source/drain region out of said channel forming regions; forming a first gate insulator on a surface of the first channel forming semiconductor region between each of said second channel forming regions; forming a second gate electrode at one side on said second gate insulator at one side; forming a second gate electrode at the other side on said second gate insulator at the other side; forming a first gate electrode on said first gate insulator, wherein said second insulators at one and the other sides are provided with carrier charge trapping means; and forming an insulating material at least on end surfaces of one gate electrode out of said first and second gate electrodes wherein said insulating material is of a side-wall insulating material left by anisotropically etching said insulating layer material which is uniformly formed on the main surface of said substrate.

Claim 23

The method of making a nonvolatile memory cell comprising: providing a pair of source and drain regions formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; providing a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; providing a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers and wherein a carrier injected from said source region to said second channel forming region is injected in said second gate insulator by getting over a potential barrier between said first layer of said second gate insulator and said second channel forming region; forming a first gate electrode on said first gate insulator; forming a second gate electrode on said second gate insulator; forming an insulating material at least on end surfaces of one gate electrode out of said first and second gate electrodes; forming a first potential feeding means which feeds to said drain region the first potential to supply to said carrier such energy that said carrier may get over said potential barrier formed between said second channel forming region and said first layer of said second gate insulator; and forming a second potential feeding means which feeds to said second gate electrode the potential to form an auxiliary electric field capable of having said carrier which has overcome said potential barrier reached said second layer of said second gate insulator.

Claim 24

The method of making a nonvolatile memory cell comprising: providing a pair of source and drain regions formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; providing a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; providing a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers and wherein a carrier injected from said source region to said second channel forming region is injected in said second gate insulator by getting over a potential barrier between said first layer of said second gate insulator and said second channel forming region; forming a first gate electrode on said first gate insulator; forming a second gate electrode on said second gate insulator; forming an insulating material at least on end surfaces of one gate electrode out of said first and second gate electrodes; forming a first potential feeding means which feeds to said drain region the first potential to supply to said carrier such energy that said carrier may get over said potential barrier formed between said second channel forming region and said first layer of said second gate insulator; and forming a second potential feeding means which feeds to said second gate electrode the potential to form an auxiliary electric field capable of having said carrier which has overcome said potential barrier reached said second layer of said second gate insulator.

Claim 32

The method of making a nonvolatile memory cell comprising: forming a pair of source/drain regions in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate, said channel forming semiconductor regions comprising a first channel forming semiconductor region, a second channel forming semiconductor region at one side and a second channel forming semiconductor region at the other side; forming a second gate insulator at one side on a surface of said second channel forming semiconductor region at one side adjacent to a source/drain region at one side out of said channel forming semiconductor regions; forming a second gate insulator at the other side on a surface of said second channel forming semiconductor region at the other side adjacent to the other source/drain region out of said channel forming regions wherein said second gate insulators and at one and the other sides are at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with said second channel forming region; (b) a third layer forming a potential barrier at the interface with one of said second gate electrodes; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers; forming a first gate insulator on a surface of the first channel forming semiconductor region between each of said second channel forming regions; forming a second gate electrode at one side on said second gate insulator at one side; forming a second gate electrode at the other side on said second gate insulator at the other side; forming a first gate electrode on said first gate insulator, wherein said second insulators at one and the other sides are provided with carrier charge trapping means; and forming an insulating material at least on end surfaces of one gate electrode out of said first and second gate electrodes.

Claim 33

The method of making a nonvolatile memory cell comprising: forming a pair of source/drain regions in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate, said channel forming semiconductor regions comprising a first channel forming semiconductor region, a second channel forming semiconductor region at one side and a second channel forming semiconductor region at the other side; forming a second gate insulator at one side on a surface of said second channel forming semiconductor region at one side adjacent to a source/drain region at one side out of said channel forming semiconductor regions; forming a second gate insulator at the other side on a surface of said second channel forming semiconductor region at the other side adjacent to the other source/drain region out of said channel forming regions wherein said second gate insulators and at one and the other sides are at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with said second channel forming region; (b) a third layer forming a potential barrier at the interface with one of said second gate electrodes; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers; forming a first gate insulator on a surface of the first channel forming semiconductor region between each of said second channel forming regions; forming a second gate electrode at one side on said second gate insulator at one side; forming a second gate electrode at the other side on said second gate insulator at the other side; forming a first gate electrode on said first gate insulator, wherein said second insulators at one and the other sides are provided with carrier charge trapping means; and forming an insulating material at least on end surfaces of one gate electrode out of said first and second gate electrodes.