Double cycle lock approach in delay lock loop circuit

Claim 2

A delay lock loop circuit for a synchronous memory system comprising: a first path including a first adjustable delay unit circuit for receiving an external clock signal and generating an output clock signal which corresponds to the external clock signal delayed by a delay time provided by a first delay unit circuit; a feedback path including a phase detector and a register, the phase detector for detecting the phase difference between the external clock signal and a feedback clock signal corresponding to the generated output clock signal, the register for storing a delay value for controlling the first delay unit circuit and determining the delay time, the phase detector generating control signals dependent on the detected phase difference, the control signals for controlling the register to adjust the delay value stored in the register to obtain a desired delay value wherein no phase difference is detected; a controller for providing a control signal having a first enable state and a second disable state; a second delay unit circuit including a plurality of individual delay elements each having its enable/disable port coupled to the control signal, a first delay element of the plurality of elements having its input coupled to a fixed voltage corresponding to a first logic state; wherein, upon system start-up and when the control signal is switched from its disable state to its enable state in response to the rising edge of the first cycle of the feedback clock signal, the individual delay elements are enabled causing the fixed voltage to begin to propagate through the plurality of the individual delay elements; and when the control signal is switched to its disable state in response to the rising edge of the second cycle of the external clock signal occurring subsequent to the rising edge of the first cycle of the feedback clock signal the plurality of individual delay elements are disabled causing the desired delay value to be established on the output of the second delay unit circuit; wherein, the second delay unit circuit is used to pre-set the register with the desired delay value.

Claim 3

The circuit as described in claim 1 wherein the register is a shift register.

Claim 4

The circuit as described in claim 1 wherein the first and second delay units have identical designs.

Claim 5

The circuit as described in claim 1 wherein the memory system is a synchronous dynamic RAM (SDRAM).

Claim 6

The circuit as described in claim 4 wherein the SDRAM is designed to provide double data rate (DDR) operation.

Claim 7

The circuit as described in claim 1 wherein the controller comprises a SR latch, a first flip-flop, and a second flip-flop, the latch has its set input port (S) coupled to the feedback clock signal, its enable input port (EN) coupled to an enable signal, and its reset input port (R) coupled to the output of the second flip-flop, the input of the first flip-flop is coupled to the enable signal and each of the first and second flip-flops have their clock inputs coupled to the external clock signal, the enable signal being applied upon start up of the system, wherein the first and second flip-flops function to reset the SR latch on the rising edge of the second cycle of the external clock signal.

Claim 8

A synchronous memory system comprising: an array of memory cells for providing data when synchronously accessed; an output buffer for receiving the data from the memory cells and in response to a delayed output clock signal outputting the data from the memory system; a delay lock loop circuit for generating the delayed output clock signal in response to an external clock signal such that the memory system synchronously outputs the data from the buffer upon at least one of the rising and falling edges of the external clock, the delay lock loop circuit comprising: a first path including a first adjustable delay unit circuit for receiving an external clock signal and generating the delayed output clock signal which is the external clock signal delayed by an amount of delay time provided by the first delay unit circuit; a feedback path including a phase detector and a register, the phase detector for detecting the phase difference between the external clock signal and a feedback clock signal corresponding to the delayed output clock signal, the register for storing a delay value for controlling the first delay unit circuit and determining delay time, the phase detector generating control signals for controlling the register dependent on the detected phase difference, so as to adjust the delay value stored in the register to obtain a desired delay value wherein no phase difference is detected; a controller for providing a control signal having a first enable state and a second disable state; a second delay unit circuit including a plurality of individual delay elements each having its enable/disable port coupled to the control signal, a first delay element of the plurality of elements having its input coupled to a fixed voltage corresponding to a first logic state; wherein, upon system start-up when the control signal is switched from its disable state to its enable state in response to the rising edge of the first cycle of the feedback clock signal, the individual delay elements are enabled causing the fixed voltage to begin to propagate through the plurality of the second delay unit elements; and when the control signal is switched to its disable state in response to the rising edge of the second cycle of the external clock signal occurring subsequent to the first rising edge the plurality of delay elements are disabled causing the desired delay value established on the output of the second delay unit circuit; wherein, the second delay unit circuit is used to pre-set the register with the desired delay value.

Claim 9

A synchronous memory system comprising: an array of memory cells for providing data when synchronously accessed; an output buffer for receiving the data from the memory cells and in response to a delayed output clock signal outputting the data from the memory system; a delay lock loop circuit for generating the delayed output clock signal in response to an external clock signal such that the memory system synchronously outputs the data from the buffer upon at least one of the rising and falling edges of the external clock, the delay lock loop circuit comprising: a first path including a first adjustable delay unit circuit for receiving an external clock signal and generating the delayed output clock signal which is the external clock signal delayed by an amount of delay time provided by the first delay unit circuit; a feedback path including a phase detector and a register, the phase detector for detecting the phase difference between the external clock signal and a feedback clock signal corresponding to the delayed output clock signal, the register for storing a delay value for controlling the first delay unit circuit and determining delay time, the phase detector generating control signals for controlling the register dependent on the detected phase difference, so as to adjust the delay value stored in the register to obtain a desired delay value wherein no phase difference is detected; a controller for providing a control signal having a first enable state and a second disable state; a second delay unit circuit including a plurality of individual delay elements each having its enable/disable port coupled to the control signal, a first delay element of the plurality of elements having its input coupled to a fixed voltage corresponding to a first logic state; wherein, upon system start-up when the control signal is switched from its disable state to its enable state in response to the rising edge of the first cycle of the feedback clock signal, the individual delay elements are enabled causing the fixed voltage to begin to propagate through the plurality of the second delay unit elements; and when the control signal is switched to its disable state in response to the rising edge of the second cycle of the external clock signal occurring subsequent to the first rising edge the plurality of delay elements are disabled causing the desired delay value established on the output of the second delay unit circuit; wherein, the second delay unit circuit is used to pre-set the register with the desired delay value.

Claim 10

The system as described in claim 7 wherein the register is a shift register.

Claim 11

The system as described in claim 7 wherein the first and second delay units have identical designs.

Claim 12

The system as described in claim 7 wherein the memory system is a synchronous dynamic RAM (SDRAM).

Claim 13

The circuit as described in claim 10 wherein the SDRAM is designed to provide double data rate (DDR) operation.

Claim 14

The circuit as described in claim 7 wherein the controller comprises an SR latch, a first flip-flop, and a second flip-flop, the latch has its set input port (S) coupled to the feedback clock signal, its enable input port (EN) coupled to an enable signal, and its reset input port (R) coupled to the output of the second flip-flop, the input of the first flip-flop is coupled to the enable signal and each of the first and second flip-flops have their clock inputs coupled to the external clock signal, the enable signal being applied upon start up of the system, wherein the first and second flip-flops function to reset the SR latch on the rising edge of the second cycle of the external clock signal.