Method and apparatus for a logic circuit design tool

Claim 2

A design tool to design a logic circuit, comprising: a syntax statement, said syntax statement further comprises encoded information that specifies a logical function of a logic circuit having a plurality of transistors arranged in a configuration that accomplishes said logical function, said configuration further includes a plurality of internal nodes that includes a virtual ground node and one or more evaluate nodes; wherein said encoded information further comprises a gate expression that includes at least one of the following: a first operator that assigns a signal value to control the gate of a specific transistor of said plurality of transistors, a second operator that indicates the position of at least two specific transistors of said plurality of transistors relative to each other within said configuration, or a third operator that either assigns a value to a specific internal node or indicates the position of a specific transistor of said plurality of transistors relative to said virtual ground node; and a compiler that processes and decodes said syntax statement, said compiler produces from said syntax statement a behavioral model of the circuit and a physical circuit description of said logic circuit.

Claim 3

The tool of claim 1 wherein said syntax statement further comprises a signal output variable that identifies the desired output of said logic circuit and a gate operator that assigns said signal output variable to the result of said gate expression.

Claim 4

The tool of claim 1 wherein said gate expression further comprises a mux select expression that specifies said configuration as one of the following: a top-select mux, a bottom-select mux, or a hybrid of top-select and bottom-select muxes.

Claim 5

The tool of claim 1 wherein said gate expression further comprises a multiple output expression that specifies said configuration as having more than one output signal.

Claim 6

The tool of claim 1 wherein said gate expression further comprises a capacitance isolation expression that specifies at least two of said plurality of transistors that couple to a complex output driver.

Claim 7

The tool of claim 1 wherein said gate expression further comprises a shared node expression that combines two or more upwardly equivalent internal nodes or two or more downwardly equivalent internal nodes within said configuration.

Claim 8

The tool of claim 1 wherein said logic circuit further comprises a N-NARY logic circuit comprising a precharge circuit, an evaluation circuit, a plurality of output drivers, and a shared logic tree circuit having multiple evaluation paths wherein one and only one evaluation path is active during an evaluation cycle, said shared logic tree circuit receives one or more 1-of-N input signals and produces one or more 1-of-N output signals.

Claim 11

The system of claim 8 wherein said syntax statement further comprises a signal output variable that identifies the desired output of said logic circuit and a gate operator that assigns said signal output variable to the result of said gate expression.

Claim 12

The system of claim 8 wherein said gate expression further comprises a mux select expression that specifies said configuration as one of the following: a top-select mux, a bottom-select mux, or a hybrid of top-select and bottom-select muxes.

Claim 13

The system of claim 8 wherein said gate expression further comprises a multiple output expression that specifies said configuration as having more than one output signal.

Claim 14

The system of claim 8 wherein said gate expression further comprises a capacitance isolation expression that specifies at least two of said plurality of transistors that couple to a complex output driver.

Claim 15

The system of claim 8 wherein said gate expression further comprises a shared node expression that combines two or more upwardly equivalent internal nodes or two or more downwardly equivalent internal nodes within said configuration.

Claim 16

The system of claim 8 wherein said logic circuit is a N-NARY logic circuit comprising a precharge circuit, an evaluation circuit, a plurality of output drivers, and a shared logic tree circuit having multiple evaluation paths wherein one and only one evaluation path is active during an evaluation cycle, said shared logic tree circuit receives one or more 1-of-N input signals and produces one or more 1-of-N output signals.

Claim 19

The method of claim 15 wherein said syntax statement further comprises a signal output variable that identifies the desired output of said logic circuit and a gate operator that assigns said signal output variable to the result of said gate expression.

Claim 20

The method of claim 15 wherein said gate expression further comprises a mux select expression that specifies said configuration as one of the following: a top-select mux, a bottom-select mux, or a hybrid of top-select and bottom-select muxes.

Claim 21

The method of claim 15 wherein said gate expression further comprises a multiple output expression that specifies said configuration as having more than one output signal.

Claim 22

The method of claim 15 wherein said gate expression further comprises a capacitance isolation expression that specifies at least two of said plurality of transistors that couple to a complex output driver.

Claim 23

The method of claim 15 wherein said gate expression further comprises a shared node expression that combines two or more upwardly equivalent internal nodes or two or more downwardly equivalent internal nodes within said configuration.

Claim 24

The method of claim 15 wherein said logic circuit is a N-NARY logic circuit comprising a precharge circuit, an evaluation circuit, a plurality of output drivers, and a shared logic tree circuit having multiple evaluation paths wherein one and only one evaluation path is active during an evaluation cycle, said shared logic tree circuit receives one or more 1-of-N input signals and produces one or more 1-of-N output signals.

Claim 27

The method of claim 22 wherein said syntax statement further comprises a signal output variable that identifies the desired output of said logic circuit and a gate operator that assigns said signal output variable to the result of said gate expression.

Claim 28

The method of claim 22 wherein said gate expression further comprises a mux select expression that specifies said configuration as one of the following: a top-select mux, a bottom-select mux, or a hybrid of top-select and bottom-select muxes.

Claim 29

The method of claim 22 wherein said gate expression further comprises a multiple output expression that specifies said configuration as having more than one output signal.

Claim 30

The method of claim 22 wherein said gate expression further comprises a capacitance isolation expression that specifies at least two of said plurality of transistors that couple to a complex output driver.

Claim 31

The method of claim 22 wherein said gate expression further comprises a shared node expression that combines two or more upwardly equivalent internal nodes or two or more downwardly equivalent internal nodes within said configuration.

Claim 32

The method of claim 22 wherein said logic circuit is a N-NARY logic circuit comprising a precharge circuit, an evaluation circuit, a plurality of output drivers, and a shared logic tree circuit having multiple evaluation paths wherein one and only one evaluation path is active during an evaluation cycle, said shared logic tree circuit receives one or more 1-of-N input signals and produces one or more 1-of-N output signals.

Claim 33

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of designing logic circuits, said method comprising: developing a syntax statement that comprises encoded information that specifies a logical function of a logic circuit and encoded information specifying said logic circuit as having a plurality of transistors arranged in a configuration that accomplishes said logical function, said configuration further includes a plurality of internal nodes that includes a virtual ground node and one or more evaluate nodes; wherein said encoded information further comprises a gate expression that includes at least one of the following: a first operator that assigns a signal value to control the gate of a specific transistor of said plurality of transistors, a second operator that indicates the position of at least two specific transistors of said plurality of transistors relative to each other within said configuration, or a third operator that either assigns a value to a specific internal node or indicates the position of a specific transistor of said plurality of transistors relative to said virtual ground node; and processing and decoding said syntax statement using a compiler, said compiler produces from said syntax statement a behavioral model of the circuit and a physical circuit description of said logic circuit.

Claim 34

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of designing logic circuits, said method comprising: developing a syntax statement that comprises encoded information that specifies a logical function of a logic circuit and encoded information specifying said logic circuit as having a plurality of transistors arranged in a configuration that accomplishes said logical function, said configuration further includes a plurality of internal nodes that includes a virtual ground node and one or more evaluate nodes; wherein said encoded information further comprises a gate expression that includes at least one of the following: a first operator that assigns a signal value to control the gate of a specific transistor of said plurality of transistors, a second operator that indicates the position of at least two specific transistors of said plurality of transistors relative to each other within said configuration, or a third operator that either assigns a value to a specific internal node or indicates the position of a specific transistor of said plurality of transistors relative to said virtual ground node; and processing and decoding said syntax statement using a compiler, said compiler produces from said syntax statement a behavioral model of the circuit and a physical circuit description of said logic circuit.

Claim 35

The program storage device of claim 29 wherein said syntax statement further comprises a signal output variable that identifies the desired output of said logic circuit and a gate operator that assigns said signal output variable to the result of said gate expression.

Claim 36

The program storage device of claim 29 wherein said gate expression further comprises a mux select expression that specifies said configuration as one of the following: a top-select mux, a bottom-select mux, or a hybrid of top-select and bottom-select muxes.

Claim 37

The program storage device of claim 29 wherein said gate expression further comprises a multiple output expression that specifies said configuration as having more than one output signal.

Claim 38

The program storage device of claim 29 wherein said gate expression further comprises a capacitance isolation expression that specifies at least two of said plurality of transistors that couple to a complex output driver.

Claim 39

The program storage device of claim 29 wherein said gate expression further comprises a shared node expression that combines two or more upwardly equivalent internal nodes or two or more downwardly equivalent internal nodes within said configuration.

Claim 40

The program storage device of claim 29 wherein said logic circuit is a N-NARY logic circuit comprising a precharge circuit, an evaluation circuit, a plurality of output drivers, and a shared logic tree circuit having multiple evaluation paths wherein one and only one evaluation path is active during an evaluation cycle, said shared logic tree circuit receives one or more 1-of-N input signals and produces one or more 1-of-N output signals.