US6385671B1
Expired / Lapsed
US
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Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field
Assignee: Intel Corp
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Filing: 1999-03-29
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Granted: 2002-05-07
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Expires: 2019-03-29
Abstract
Abstract The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.
Inventors
- 👤 Mikal C. Hunsaker
- 👤 Darren L. Abramson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:30
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/9084; H04L49/9089; H04L49/9094; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; H04L49/901
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
102 words
A method for processing data, the method comprising: generating a self-ID code by a counter, the counter incrementing the self-ID code after a bus reset; formatting a start-of-packet (SOP) message to contain a self-ID field, the SOP message corresponding to a packet received from a direct memory access (DMA) engine, the self-ID field corresponding to the self-ID code; writing the SOP message into a fist-in-first-out (FIFO); comparing the self-ID field of a message read from the FIFO with the self-ID code; and flushing the packet if the self-ID field of the message read from the FIFO is different than the self-ID code.
Claim 2
Independent Claim
102 words
A method for processing data, the method comprising: generating a self-ID code by a counter, the counter incrementing the self-ID code after a bus reset; formatting a start-of-packet (SOP) message to contain a self-ID field, the SOP message corresponding to a packet received from a direct memory access (DMA) engine, the self-ID field corresponding to the self-ID code; writing the SOP message into a fist-in-first-out (FIFO); comparing the self-ID field of a message read from the FIFO with the self-ID code; and flushing the packet if the self-ID field of the message read from the FIFO is different than the self-ID code.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein formatting the SOP message includes merging the self-ID code with SOP information.
Claim 4
Dependent Claim
33 words
The method of claim 1 further comprises: if the self-ID field of the message is identical to the self-ID code, transferring the packet to a link interface for transmission to a serial bus.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein the counter wraps around to zero after reaching a maximum value.
Claim 6
Dependent Claim
16 words
The method of claim 2 wherein the SOP information includes DMA context code and transmission code.
Claim 7
Dependent Claim
13 words
The method of claim 2 wherein the SOP information includes a self-ID code.
Claim 8
Dependent Claim
13 words
The method of claim 3 wherein the serial bus is a 1394 bus.
Claim 9
Dependent Claim
16 words
The method of claim 1 wherein the DMA engine is an asynchronous transmit (AT) DMA engine.
Claim 10
Independent Claim
133 words
An apparatus for processing data, the apparatus comprising: a counter to generate a self-ID code, the counter incrementing the self-ID code after a bus reset; a formatter coupled to the counter to format a start-of-packet (SOP) message to contain a self-ID field, the SOP message corresponding to a packet received from a direct memory access (DMA) engine, the self-ID field corresponding to the self-ID code; a fist-in-first-out (FIFO) coupled to the formatter to store the SOP message and the packet; a comparator coupled to the FIFO to compare the self-ID field of a message read from the FIFO with the self-ID code; and a control circuit coupled to the FIFO, the control circuit flushing the packet if the self-ID field of the message read from the FIFO is different than the self-ID code.
Claim 11
Independent Claim
133 words
An apparatus for processing data, the apparatus comprising: a counter to generate a self-ID code, the counter incrementing the self-ID code after a bus reset; a formatter coupled to the counter to format a start-of-packet (SOP) message to contain a self-ID field, the SOP message corresponding to a packet received from a direct memory access (DMA) engine, the self-ID field corresponding to the self-ID code; a fist-in-first-out (FIFO) coupled to the formatter to store the SOP message and the packet; a comparator coupled to the FIFO to compare the self-ID field of a message read from the FIFO with the self-ID code; and a control circuit coupled to the FIFO, the control circuit flushing the packet if the self-ID field of the message read from the FIFO is different than the self-ID code.
Claim 12
Dependent Claim
15 words
The apparatus of claim 9 wherein the formatter merges the self-ID code with SOP information.
Claim 13
Dependent Claim
35 words
The apparatus of claim 9 wherein the control circuit transfers the packet to a link interface for transmission to a serial bus if the self-ID field of the message is identical to the self-ID code.
Claim 14
Dependent Claim
17 words
The apparatus of claim 9 wherein the counter wraps around to zero after reaching a maximum value.
Claim 15
Dependent Claim
16 words
The apparatus of claim 10 wherein the SOP information includes DMA context code and transmission code.
Claim 16
Dependent Claim
13 words
The apparatus of claim 10 wherein the SOP information includes a self-ID code.
Claim 17
Dependent Claim
13 words
The apparatus of claim 11 wherein the serial bus is a 1394 bus.
Claim 18
Dependent Claim
16 words
The apparatus of claim 1 wherein the DMA engine is an asynchronous transmit (AT) DMA engine.
Claim 19
Independent Claim
178 words
A system comprising: a first bus; a processor coupled to the bus; a memory coupled to the processor; and a bridge couple to the first bus and a second bus via a physical link device, the bridge managing a transfer of a packet of data between the second bus and the processor, the bridge comprising: a direct memory access (DMA) engine, a counter to generate a self-ID code, the counter incrementing the self-ID code after a bus reset, a formatter coupled to the counter to format a start-of-packet (SOP) message to contain a self-ID field, the SOP message corresponding to the packet, the self-ID field corresponding to the self-ID code, a fist-in-first-out (FIFO) coupled to the formatter to store the SOP message and the packet, a comparator coupled to the FIFO to compare the self-ID field of a message read from the FIFO with the self-ID code, and a control circuit coupled to the FIFO, the control circuit flushing the packet if the self-ID field of the message read from the FIFO is different than the self-ID code.
Claim 20
Independent Claim
178 words
A system comprising: a first bus; a processor coupled to the bus; a memory coupled to the processor; and a bridge couple to the first bus and a second bus via a physical link device, the bridge managing a transfer of a packet of data between the second bus and the processor, the bridge comprising: a direct memory access (DMA) engine, a counter to generate a self-ID code, the counter incrementing the self-ID code after a bus reset, a formatter coupled to the counter to format a start-of-packet (SOP) message to contain a self-ID field, the SOP message corresponding to the packet, the self-ID field corresponding to the self-ID code, a fist-in-first-out (FIFO) coupled to the formatter to store the SOP message and the packet, a comparator coupled to the FIFO to compare the self-ID field of a message read from the FIFO with the self-ID code, and a control circuit coupled to the FIFO, the control circuit flushing the packet if the self-ID field of the message read from the FIFO is different than the self-ID code.
Claim 21
Dependent Claim
15 words
The system of claim 17 wherein the formatter merges the self-ID code with SOP information.
Claim 22
Dependent Claim
35 words
The system of claim 17 wherein the control circuit transfers the packet to a link interface for transmission to a serial bus if the self-ID field of the message is identical to the self-ID code.
Claim 23
Dependent Claim
17 words
The system of claim 17 wherein the counter wraps around to zero after reaching a maximum value.
Claim 24
Dependent Claim
16 words
The system of claim 18 wherein the SOP information includes DMA context code and transmission code.
Claim 25
Dependent Claim
13 words
The system of claim 18 wherein the SOP information includes a self-ID code.
Claim 26
Dependent Claim
13 words
The system of claim 19 wherein the serial bus is a 1394 bus.
Claim 27
Dependent Claim
16 words
The system of claim 17 wherein the DMA engine is an asynchronous transmit (AT) DMA engine.
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| 3.5 Years (Year 4) | 2005-05-06 | 2005-11-05 | 2006-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-06 | 2009-11-05 | 2010-05-07 | $3760.00 | Window Closed / Lapsed |
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