Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Claim 2

A nonvolatile memory cell comprising: a pair of source and drain regions formed in a main surface of a substrate and separated there between by channel forming semiconductor regions in said main surface of said substrate; a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator, wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers.

Claim 3

A nonvolatile memory cell according to claim 1 wherein a carrier injected from said source region to a second channel forming region is injected in the second gate insulator by getting over a potential barrier between said first layer of said second gate insulator and said second channel forming region.

Claim 4

A nonvolatile memory cell according to claim 1 and further comprising: a first potential feeding means which feeds to said drain region the first potential to supply to said carrier such energy that said carrier may get over the potential barrier formed between said second channel forming region and the first layer of the second gate insulator; and a second potential feeding means which feeds to the second gate electrode the potential to form an auxiliary electric field capable of having said carrier which has overcome the potential barrier reached said second layer of the second gate insulator.

Claim 5

A nonvolatile memory cell according to claims 1 wherein an insulating material is formed at least on end surfaces of one gate electrode out of said first and second gate electrodes.

Claim 6

A nonvolatile memory cell according to claim 4 wherein the insulating material formed on the end surfaces of the one gate electrode is of a side-wall insulating material left anisotropically etching the insulating material formed uniformly on the main surface of the substrate.

Claim 7

A nonvolatile memory cell according to claim 4 wherein the insulating material formed on the end surfaces of the one gate electrode is of an oxide film formed by oxidizing said one gate electrode.

Claim 8

A nonvolatile memory cell as claimed in claim 1 wherein an insulator is formed to insulate said first gate electrode from second gate electrode each other.

Claim 9

A nonvolatile memory cell as claimed in claim 1 wherein said second gate electrode and the second gate insulator thereof are extended to cover a surface and an end surface at the drain side of said first gate electrode.

Claim 10

A nonvolatile memory cell as claimed in claim 1 wherein said first gate electrode and the first gate insulator thereof are extended to cover a surface and an end surface at the source side of said second gate electrode.

Claim 11

A nonvolatile memory cell as claimed in claim 1 wherein said first and second gate electrodes are mutually insulated by said second gate insulator extended to a gap between said electrodes.

Claim 12

A nonvolatile memory cell according to claim 1 wherein carrier tunnel probability of said first layer of said second gate insulator is lower than carrier tunnel probability of said third layer.

Claim 13

A nonvolatile memory cell according to claim 1 wherein the carrier tunnel probability of said first layer of said second gate insulator is higher than carrier tunnel probability of said third layer.

Claim 14

The method of claim 12 wherein the thickness of said first layer is made thinner than the thickness of said third layer.

Claim 15

A nonvolatile memory cell according to claim 1 wherein impurity concentration of the second channel forming region of said channel forming regions is higher than impurity concentration of the first channel forming region.

Claim 16

A method of programming a nonvolatile memory cell as claimed in claim 1 wherein: carrier injection from said second channel forming region to the second gate insulator is conducted by applying a predetermined potential to said drain region so that energy to get over a potential barrier between the second channel forming region and said first layer of said second insulator may be supplied to a carrier and by applying to the second gate electrode the potential to supply an auxiliary electric field to the carrier having overcome said potential barrier, and carrier extraction from said second gate insulator is conducted by applying to said second gate electrode a potential whose polarity is the same as said potential applied when injecting said carrier therein so that the electric field enabling the carrier to conduct by tunnel-transition across a potential barrier formed between the second layer and the third layer of said second gate insulator may be supplied to said third layer.

Claim 17

A nonvolatile memory cell comprising: a pair of source/drain regions at one side and at the other side formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; said channel forming semiconductor regions comprising a first channel forming semiconductor region, a second channel forming semiconductor region at one side and a second channel forming semiconductor region at the other side; a second gate insulator at one side formed on a surface of the second channel forming semiconductor region at one side adjacent to the source/drain region at one side; a second gate insulator at the other side formed on a surface of the second channel forming semiconductor region at the other side adjacent to the source/drain region at the other side; said second insulators at one side and the other side being provided with carrier charge trapping means; a first gate insulator formed on a surface of the first channel forming semiconductor region between each of said second channel forming regions; a second gate electrode at one side formed on said second gate insulator at one side; a second gate electrode at the other side formed on said second gate insulator at the other side; and a first gate electrode formed on said first gate insulator.

Claim 18

A nonvolatile memory cell comprising: a pair of source/drain regions at one side and at the other side formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; said channel forming semiconductor regions comprising a first channel forming semiconductor region, a second channel forming semiconductor region at one side and a second channel forming semiconductor region at the other side; a second gate insulator at one side formed on a surface of the second channel forming semiconductor region at one side adjacent to the source/drain region at one side; a second gate insulator at the other side formed on a surface of the second channel forming semiconductor region at the other side adjacent to the source/drain region at the other side; said second insulators at one side and the other side being provided with carrier charge trapping means; a first gate insulator formed on a surface of the first channel forming semiconductor region between each of said second channel forming regions; a second gate electrode at one side formed on said second gate insulator at one side; a second gate electrode at the other side formed on said second gate insulator at the other side; and a first gate electrode formed on said first gate insulator.

Claim 19

A nonvolatile memory cell according to claim 16 wherein a carrier injected from said source/drain region at one side to the second channel forming region at the other side is injected in the second gate insulator at the other side by getting over a potential barrier between said second gate insulator at the other side and the second channel forming region at the other side.

Claim 20

A nonvolatile memory cell according to claim 16 wherein a carrier injected from said source/drain region at the other side to the second channel forming region at one side is injected in said second gate insulator at one side by getting over the potential barrier between said second gate insulator at one side and the second channel forming region at one side.

Claim 21

A nonvolatile memory cell according to claim 16 wherein an insulating material is formed at least on end surfaces of one gate electrode out of said first and second gate electrodes.

Claim 22

A nonvolatile memory cell according to claim 19 wherein the insulating material formed on the end surface of the one gate electrode is of a side-wall insulating material left by anisotropically etching the insulating layer material which is uniformly formed on the main surface of the substrate.

Claim 23

A nonvolatile memory cell according to claim 19 wherein the insulating material formed on the end surface of the one gate electrode is of an oxide film formed by oxidizing said one gate electrode.

Claim 24

A nonvolatile memory cell as claimed in claim 16 wherein an insulator is formed to insulate said first gate electrode from second gate electrodes each other.

Claim 25

A nonvolatile memory cell as claimed in claim 16 wherein said second gate electrode and gate insulator thereof at one side are extended to cover a surface and end surface of said first gate electrode at one side, and said second gate electrode and gate insulator thereof at the other side are extended to cover a surface and end surface of said first gate electrode at the other side.

Claim 26

A nonvolatile memory cell according to claim 16 wherein said first gate electrode and insulator thereof are extended to cover a surface and end surface of each second gate electrode adjacent thereto at one and the other sides.

Claim 27

A nonvolatile memory cell according to claim 16 wherein said second gate insulators at one side and the other side are extended to a gap between said first gate electrode and each of second gate electrodes.

Claim 28

A nonvolatile memory cell according to claim 16 wherein impurity concentration of each of the second channel forming region in said channel forming regions is higher than impurity concentration of the first channel forming region.

Claim 29

A nonvolatile memory cell as claimed in claim 16 wherein said second gate insulators and at one and the other sides are at least of a three-layer structure including: (a) a first layer forming a potential barrier at an interface with one of the second channel forming regions; (b) a third layer forming a potential barrier at the interface with one of the second gate electrodes; and (c) a second layer forming said carrier trapping means at least at one location out of an inside portion of the second layer itself and interfaces with said first and third layers.

Claim 30

A nonvolatile memory cell according to claim 27 wherein carrier tunnel probability of said first layer of said second gate insulators is lower than carrier tunnel probability of said third layer.

Claim 31

A nonvolatile memory cell according to claim 27 wherein carrier tunnel probability of said first layer of said second gate insulators is higher than carrier tunnel probability of said third layer.

Claim 32

The method of claim 29 wherein the thickness of said first layer is made thinner than the thickness of said third layer.

Claim 33

A method of programming a nonvolatile memory cell as claimed in claim 27 wherein: carrier injection from said second channel forming region at one side to the second gate insulator at one side is conducted by applying a predetermined potential to said source/drain region at one side so that energy to get over a potential barrier between the second channel forming region at one side and said first layer of said second insulator at one side may be supplied to a carrier and by applying to the second gate electrode at one side the potential to supply an auxiliary electric field to the carrier having overcome said potential barrier, and carrier extraction from-said second gate insulator at one side is conducted by applying to said second gate electrode at one side a potential whose polarity is the same as said potential applied when injecting said carrier therein so that the electric field enabling the carrier to perform tunnel-transition across a potential barrier formed between the second layer and the third layer of the second gate insulator at one side may be supplied to said third layer.

Claim 34

A method of programming a nonvolatile memory cell as claimed in claim 27 wherein: carrier injection from said second channel forming region at the other side to a second gate insulator at the other side is conducted by applying a predetermined potential to said source/drain region at the other side so that energy to get over a potential barrier between the second channel forming region at the other side and the first layer of said second insulator at the other side may be supplied to a carrier and by applying to the second gate electrode the potential to supply an auxiliary electric field to the carrier having overcome said potential barrier, and carrier extraction from said second gate insulator at the other side is conducted by applying to said second gate electrode at the other side a potential whose polarity is the same as said potential applied when injecting said carrier therein so that the electric field enabling the carrier to perform tunnel-transition across of a potential barrier formed between the second layer and the third layer of the second gate insulator at the other side may be applied to said third layer.

Claim 35

A nonvolatile memory array configured by disposing in the form of a matrix a nonvolatile memory cell as claimed in claim 16 comprising: a plurality of bit lines (L B ) each one of which commonly connects in the direction of a column each of the source/drain regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same row, a plurality of first control lines (L S a) each one of which connects each of the second gate electrodes at one side of the nonvolatile memory cells disposed on a same column; and a plurality of second control lines (L S b) each one of which connects each of the second gate electrodes at the other side of the nonvolatile memory cells disposed on a same column.

Claim 36

A non-volatile memory array according to claim 33 wherein both ends of said first gate electrode and an insulator are formed to cover at least end portion and end surface of each of said second gate electrodes at one side and at the other side and wherein said first gate electrodes of adjacent cells are interconnected across said source/drain region to make said word line.

Claim 37

A non-volatile memory array according to claim 34 wherein a side wall insulator is provided on an end surface of said first gate electrode.

Claim 38

A non-volatile memory array according to claim 33 wherein said first gate electrode is common with said word line (L W ) and further is extended over said second gate electrodes and insulated by an insulator formed on a surface of each of said second gate electrodes and by a side-wall insulator on a side surface of each of said second gate electrodes.

Claim 39

A non-volatile memory array according to claim 33 wherein: said second gate insulator is extended to a gap between said first gate electrode and said second gate electrodes; said second gate electrodes at one and the other sides of said first gate electrodes are formed as a pair of side-walls on said second gate insulator; and said word line (L W ) over said second gate electrodes is connected to an upper portion of said first gate electrode.

Claim 40

A non-volatile memory array according to claim 37 wherein an oxide film on an end surface of said first gate electrode is provided by oxidizing said first gate electrode.

Claim 41

A nonvolatile memory array configured by disposing in the form of a matrix the nonvolatile memory cells as claimed in claim l 6 comprising: a plurality of common lines (L C ) each one of which commonly connects in the direction of a column each of the source/drain regions at one side of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of bit lines (L B ) each one of which connects each of the source/drain regions at the other side of the nonvolatile memory cells disposed on a same row; a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same column, a plurality of first control lines (L S a) each one of which connects each of the second gate electrodes at one side of the nonvolatile memory cells disposed on a same column; and a plurality of second control lines (L S b) each one of which connects each of the second gate electrodes at the other side of the nonvolatile memory cells dispose on a same column.

Claim 42

A nonvolatile cell according to claim 16 wherein said second gate insulator is extended into a gap between said first gate electrode and said second gate electrodes and wherein said second gate electrodes at one said and at the other side of said first gate electrode are formed as a pair of side-walls on said second gate insulator.

Claim 43

A nonvolatile cell according to claim 16 wherein impurity concentration of said second channel forming regions is more than 4E17 atom/cm 3 .

Claim 44

A method of programming a nonvolatile memory cell as claimed in claim 16 wherein carrier injection from said second channel forming region at one side to a second gate insulator at one side is conducted by applying a predetermined potential to said source/drain region at one side so that energy to get over a potential barrier between said second channel forming region at one side and the first layer ( 132 a ) of said second insulator at one side can be supplied to a carrier and by applying to said second gate electrode at one side the potential to supply an auxiliary electric field to the carrier having overcome said potential barrier, and carrier injection from said second channel forming region at the other side to a second gate insulator at the other side is conducted by applying a predetermined potential to said source/drain region at the other side so that energy to get over a potential barrier between the second channel forming region at the other side and the first layer ( 132 a ) of said second insulator at the other side may be supplied to a carrier and by applying to said second gate electrode the potential to supply an auxiliary electric field to the carrier having overcome said potential barrier, resulting in two-bit data storage in one cell.

Claim 45

A nonvolatile memory array configured by disposing in the form of a matrix a nonvolatile memory cell said nonvolatile memory cell comprising: a pair of source and drain regions formed in a main surface of a substrate and separated there between by channel forming semiconductor regions in said main surface of said substrate; a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator, wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers; said nonvolatile memory array comprising: a plurality of bit lines (L B ) each one of which connects each of the source regions of the nonvolatile memory cells disposed on a same row; a plurality of common lines (L C ) each one of which commonly connects in the direction of column each of the drain regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of control lines (L S ) each one of which connects each of the second gate electrodes in the nonvolatile memory cells disposed on a same column; and a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same column.

Claim 46

A nonvolatile memory array configured by disposing in the form of a matrix a nonvolatile memory cell said nonvolatile memory cell comprising: a pair of source and drain regions formed in a main surface of a substrate and separated there between by channel forming semiconductor regions in said main surface of said substrate; a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator, wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers; said nonvolatile memory array comprising: a plurality of bit lines (L B ) each one of which connects each of the source regions of the nonvolatile memory cells disposed on a same row; a plurality of common lines (L C ) each one of which commonly connects in the direction of column each of the drain regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of control lines (L S ) each one of which connects each of the second gate electrodes in the nonvolatile memory cells disposed on a same column; and a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same column.

Claim 47

A method of programming a nonvolatile memory array according to claim 31 , said method comprising: applying to a selected said word line (L W ) a first potential (Vwpr 1 ) which is higher than the gate threshold voltage (Vth 1 ) of said first gate electrode ( 141 ); applying to a selected said common line (L C ) a second potential which is higher than said potential barrier voltage; applying to a selected said control line (L S ) a third potential which is higher than said potential barrier voltage minus work function difference in voltage between said second gate electrode and said second channel forming region; and applying in advance to a selected said bit line (L B ) a predetermined potential (V BP r) which is higher than the value (V WP r 1 −Vth 1 ) obtained by subtracting the threshold voltage (Vth 1 ) from said first potential (V WP r 1 ), then when programming, a fourth potential (V BP r 1 ) which is higher than the difference value (V WP r 1 −Vth 1 ) or a fifth potential (V BP r 0 ) which is lower than the difference value (V WP r 1 −Vth 1 ) being applied to said bit line depending on the content of the data stored.

Claim 48

A method of programming a nonvolatile memory array according to claim 44 further comprising: said fifth value being selected out of multi-value depending on the level of the data stored resulting in multi-value data storage.

Claim 49

A method of reading a nonvolatile memory array according to claim 43 , said method comprising: applying a first read potential (V BRD ) to selected said bit line (L B ); applying to the control line (L C ) a second read potential (V CRD ) which is higher than the smaller value out of the programmed gate threshold voltage (Vth 2 ) of said second gate electrode; and applying to the word line (L W ) a third read potential (V WRD ) which is higher than the gate threshold voltage (Vth 1 ) of said first gate electrode.

Claim 50

A method of reading a nonvolatile memory array according to claim 43 , said method comprising: applying a first read potential (V BRD ) to selected said bit line (L B ); applying to the control line (L S ) a second read potential (V CRD ) which is higher than the smaller value out of the programmed gate threshold voltage (Vth 2 ) of said second gate electrode; and applying to the word line (L W ) a third read potential (V WRD ) which is higher than the gate threshold voltage (Vth 1 ) of said first gate electrode.

Claim 51

A nonvolatile memory array configured by disposing in the form of a matrix the nonvolatile memory cells as claimed in claim 1 comprising: a plurality of bit lines (L B ) each one of which connects each of the source regions of the nonvolatile memory cells disposed on a same row; a plurality of common lines (L C ) each one of which commonly connects in the direction of a column each of the drain regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of control lines (L S ) each one of which connects each of the second gate electrodes of the nonvolatile memory cells disposed on a same row; and a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same column.

Claim 52

A method of programming a nonvolatile memory array according to claim 48 , said method comprising: applying to a selected said word line (L W ) a first potential (Vwpr 1 ) which is higher than the gate threshold voltage (Vth 1 ) of said first gate electrode; applying to a selected said common line (L C ) a second potential which is higher than said potential barrier voltage; applying to a selected said control line (L S ) a third potential which is higher than said potential barrier voltage minus work function difference in voltage between said second gate electrode and said second channel forming region; and applying in advance to a selected said bit line (L B ) a predetermined potential (V BP r) which is higher than the value (V WP ri−Vth 1 ) obtained by subtracting the threshold voltage (Vth 1 ) from said first potential (V WP r 1 ), then when programmning, a fourth potential (V BP r 1 ) which is higher than the difference value (V WP ri−Vth 1 ) or a fifth potential (V BP r 0 ) which is lower than the difference value (V WP r 1 −Vth 1 ) being applied to said bit line depending on the content of the data stored.

Claim 53

A method of programming a nonvolatile memory array according to claim 49 further comprising: said fifth value being selected out of multi-value depending on the level of the data stored, resulting multi-value data storage.

Claim 54

A nonvolatile memory array configured by disposing in the form of a matrix the nonvolatile memory cells as claimed in claim 1 comprising: a plurality of bit lines (L B ) each one of which connects each of the drain regions of the nonvolatile memory cells disposed on a same row; a plurality of common lines (L C ) each one of which commonly connects in the direction of a column each of the source regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of control lines (L S ) each one of which connects each of the second gate electrodes of the nonvolatile memory cells disposed on a same row; and a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same row.

Claim 55

A nonvolatile memory array configured by disposing in the form of a matrix nonvolatile memory cells said nonvolatile memory cell comprising: a pair of source and drain regions formed in a main surface of a substrate and separated there between by channel forming semiconductor regions in said main surface of said substrate; a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator, wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers; said nonvolatile memory array comprising: a plurality of bit lines (L B ) each one of which connects each of the drain regions of the nonvolatile memory cell disposed on a same row; a plurality of common lines (L C ) each one of which commonly connects in the direction of a column each of the source regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of control lines (L S ) each one of which connects each of the second gate electrodes of the nonvolatile memory cells disposed on a same row; and a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same column.

Claim 56

A nonvolatile memory array configured by disposing in the form of a matrix nonvolatile memory cells said nonvolatile memory cell comprising: a pair of source and drain regions formed in a main surface of a substrate and separated there between by channel forming semiconductor regions in said main surface of said substrate; a first gate insulator formed on a surface of a first channel forming region adjacent to said source region out of said channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to said drain region out of said channel forming regions; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator, wherein said second gate insulator is at least of a three-layer structure including: (a) a first layer forming a potential barrier at the interface with a channel forming region; (b) a third layer forming the potential barrier at the interface with the second gate electrode; and (c) a second layer forming a carrier trapping level at least at one location out of an inside portion of said second layer itself and interfaces with said first and third layers; said nonvolatile memory array comprising: a plurality of bit lines (L B ) each one of which connects each of the drain regions of the nonvolatile memory cell disposed on a same row; a plurality of common lines (L C ) each one of which commonly connects in the direction of a column each of the source regions of a pair of nonvolatile memory cells adjacent to the direction of a row; a plurality of control lines (L S ) each one of which connects each of the second gate electrodes of the nonvolatile memory cells disposed on a same row; and a plurality of word lines (L W ) each one of which connects each of the first gate electrodes of the nonvolatile memory cells disposed on a same column.