Semiconductor memory having transistors connected in series

Claim 2

A semiconductor memory comprising: a cell unit having first and second ends and constituted by transistors connected in series between the first and second ends; a data transferring line connected to the first end of said cell unit; and a common voltage node connected to the second end of said cell unit, wherein each transistor has substantially the same structure and a function of storing data in a nonvolatile manner, one of the transistors which is located nearest to said data transferring line and one of the transistors which is located nearest to said common voltage node are used as select gate transistors, and the transistors other than the transistors used as the select gate transistors are used as memory cells.

Claim 3

The semiconductor memory according to claim 1 , wherein the transistors used as the select gate transistors are always set in an erase state or write state.

Claim 4

The semiconductor memory according to claim 1 , wherein after all the transistors are set in the erase state, the transistors used as the select gate transistors are set in the write state.

Claim 5

The semiconductor memory according to claim 3 , wherein after the transistors used as the select gate transistors are set in the write state, data programming is executed for the transistors used as the memory cells.

Claim 6

The semiconductor memory according to claim 1 , wherein after all the transistors are set in the erase state, data programming is executed for the transistors used as the memory cells.

Claim 7

A semiconductor memory comprising: a cell unit having first and second ends and constituted by MFSFETs connected in series between the first and second ends and having substantially the same structure; a data transferring line connected to the first end of said cell unit; and a common voltage node connected to the second end of said cell unit, wherein one of the MFSFETs which is located nearest to said data transferring line and one of the MFSFETs which is located nearest to said common voltage node are used as select gate transistors, and the MFSFETs other than the MFSFETs used as the select gate transistors are used as memory cells.

Claim 8

A semiconductor memory comprising: a cell unit having first and second ends and constituted by MFSFETs connected in series between the first and second ends and having substantially the same structure; a data transferring line connected to the first end of said cell unit; and a common voltage node connected to the second end of said cell unit, wherein one of the MFSFETs which is located nearest to said data transferring line and one of the MFSFETs which is located nearest to said common voltage node are used as select gate transistors, and the MFSFETs other than the MFSFETs used as the select gate transistors are used as memory cells.

Claim 9

The semiconductor memory according to claim 6 , wherein the MFSFETs used as the select gate transistors are always set in an erase state or write state.

Claim 10

The semiconductor memory according to claim 6 , wherein after all the MFSFETs are set in the erase state, the MFSFETS used as the select gate transistors are set in the write state.

Claim 11

The semiconductor memory according to claim 8 , wherein after the MFSFETs used as the select gate transistors are set in the write state, data programming is executed for the MFSFETs used as the memory cells.

Claim 12

The semiconductor memory according to claim 6 , wherein after all the MFSFETs are set in the erase state, data programming is executed for the MFSFETs used as the memory cells.

Claim 13

The semiconductor memory according to claim 6 , wherein a low potential is applied to gate electrodes of the MFSFETs used as the memory cells, the gate electrode of an unselected MFSFET of the MFSFETs used as the memory cells is set in a floating state, a high potential is applied to a semiconductor substrate on which the MFSFETs are formed, and data erase operation is executed to a selected MFSFET of the MFSFETs used as the memory cells.

Claim 14

The semiconductor memory according to claim 6 , wherein a predetermined potential is applied to the data transferring line to charge channels of the MFSFETs used as the memory cells to an initial potential, the channels of the MFSFETs used as the memory cells are then set in the floating state, a program potential or transfer potential is applied to the gate electrodes of the MFSFETs used as the memory cells, and data programming is executed to a selected MFSFET of the MFSFETs used as the memory cells.

Claim 15

The semiconductor memory according to claim 6 , wherein a ground potential is applied to the data transferring line to set the channels of the MFSFETs used as the memory cells to a ground potential, a program potential or transfer potential is then applied to the gate electrodes of the MFSFETs used as the memory cells, and data programming is executed for a selected MFSFET of the MFSFETs used as the memory cells.

Claim 16

A semiconductor memory comprising: memory cells formed on a semiconductor region and connected in series or parallel between first and second nodes; and a select switching element formed on the semiconductor region and connected between the first node and a third node, wherein said memory cells and said select switching element each have a charge storing layer, and the charge storing layer of each of said memory cells is made of the same material as that for the charge storing layer of said select switching element and has the same thickness as that thereof.

Claim 17

A semiconductor memory comprising: memory cells formed on a semiconductor region and connected in series or parallel between first and second nodes; and a select switching element formed on the semiconductor region and connected between the first node and a third node, wherein said memory cells and said select switching element each have a charge storing layer, and the charge storing layer of each of said memory cells is made of the same material as that for the charge storing layer of said select switching element and has the same thickness as that thereof.

Claim 18

The semiconductor memory according to claim 14 , wherein each of said memory cells has a control gate electrode, said select switching element has a select gate electrode having the same structure as that of the control gate electrode, and the control gate electrodes and the select gate electrode are arranged on the same interconnection layer.

Claim 19

The semiconductor memory according to claim 14 , wherein the charge storing layer of each of said memory cells and the charge storing layer of said select switching element are separated from one another, said charge storing layer comprises a material selected from the group consisting of conductive materials including impurity-doped Si, SiGe, and Ge, and insulating materials including SiN, titanium oxide, tantalum oxide, and alumina.

Claim 20

The semiconductor memory according to claim 16 , further comprising element isolation insulating films surrounding element regions on which said memory cells and said select switching element are arranged, wherein the charge storing layers of said memory cells and the charge storing layer of said select switching element are arranged on only the element regions.

Claim 21

The semiconductor memory according to claim 16 , wherein said memory cells and said select switching element each have a gate insulating film, and the gate insulating film of said select switching element is thicker than that of each of said memory cells.

Claim 22

The semiconductor memory according to claim 14 , wherein the charge storing layer of each of said memory cells and the charge storing layer of said select switching element are combined with each other and the charge storing layer comprises one material selected from the group consisting of insulating materials including SiN, titanium oxide, tantalum oxide, and alumina.

Claim 23

The semiconductor memory according to claim 19 , further comprising element isolation insulating films surrounding element regions on which said memory cells and said select switching element are arranged, wherein the charge storing layers of said memory cells and the charge storing layer of said select switching element are arranged on only the element regions.

Claim 24

The semiconductor memory according to claim 19 , further comprising element isolation insulating films surrounding element regions on which said memory cells and said select switching element are arranged, wherein the charge storing layers of said memory cells and the charge storing layer of said select switching element are arranged on the element regions and said element isolation insulating films, respectively.

Claim 25

The semiconductor memory according to claim 19 , wherein said memory cells and said select switching element each have a gate insulating film, and the gate insulating film of said select switching element is thicker than that of each of said memory cells.

Claim 26

The semiconductor memory according to claim 14 , wherein said select switching element has a select gate electrode and a block insulating film placed between the select gate electrode and the charge storing layer of said select switching element, a current which flowed in the block insulating film is larger than that in a gate insulating film between the charge storing layer of said select switching element and the semiconductor region in write/erase operation for said select switching element.

Claim 27

The semiconductor memory according to claim 14 , wherein a threshold voltage of said select switching element change in a direction to converge to a predetermined value in erase operation.

Claim 28

The semiconductor memory according to claim 14 , wherein a threshold voltage of said select switching element change in a direction to converge to a predetermined value in write operation.

Claim 29

The semiconductor memory according to claim 14 , wherein said memory cells and said select switching element comprise field-effect transistors of a second conductivity type arranged in a well region of a first conductivity type.

Claim 30

The semiconductor memory according to claim 14 , wherein said select switching element has a select gate electrode forming above the charge storing layer, and a potential of the semiconductor region is more positive than a potential of the select gate electrode.

Claim 31

The semiconductor memory according to claim 14 , wherein the memory cells and the select switching element have a gate electrode each, which is provided on an insulating film formed on the charge storing layer, which extends at right angles to a data transferring line and which is connected to the third node.

Claim 32

A threshold voltage setting method of a semiconductor memory including a select gate transistor having a charge storing layer and memory cells having a charge storing layer, comprising the steps of: setting both a threshold voltage of the select gate transistor and a threshold voltage of the memory cells to be negative by erase operation; setting the threshold voltage of the select gate transistor to be positive by write operation; verifying whether the threshold voltage of the select gate transistor become positive; performing re-write operation if the threshold voltage of the select gate transistor has not become positive; setting the threshold voltage of the select gate transistor to be positive, and then performing write operation to make the threshold voltage of the select gate transistor fall within a set range; verifying whether the threshold voltage of the select gate transistor falls within the set range; and performing the re-write operation if the threshold voltage of the select gate transistor has not fallen within the set range.

Claim 33

A threshold voltage setting method of a semiconductor memory including a select gate transistor having a charge storing layer and memory cells having a charge storing layer, comprising the steps of: setting both a threshold voltage of the select gate transistor and a threshold voltage of the memory cells to be negative by erase operation; setting the threshold voltage of the select gate transistor to be positive by write operation; verifying whether the threshold voltage of the select gate transistor become positive; performing re-write operation if the threshold voltage of the select gate transistor has not become positive; setting the threshold voltage of the select gate transistor to be positive, and then performing write operation to make the threshold voltage of the select gate transistor fall within a set range; verifying whether the threshold voltage of the select gate transistor falls within the set range; and performing the re-write operation if the threshold voltage of the select gate transistor has not fallen within the set range.

Claim 34

The semiconductor memory according to claim 29 , wherein the threshold voltage of the select gate transistor does not become smaller than a first value in the erase operation and does not become larger than a second value in the write operation.

Claim 35

The semiconductor memory according to claim 30 , wherein the threshold voltage of said select gate transistor converges to the second value upon the re-write operation.