Semiconductor memory device utilizing access to memory area located outside main memory area

Claim 2

A semiconductor memory device comprising: a primary memory area including a plurality of memory blocks arranged in rows and columns, said plurality of memory blocks including a predetermined memory block; a secondary memory area including a hidden memory block situated in the same column as said predetermined memory block; a decision circuit selecting one of a first mode for reading first data from the primary memory area and a second mode for reading second data from the secondary memory area, said decision circuit outputting a signal when the second mode and an address of said predetermined memory block are specified; a column decoder selecting a column corresponding to a column address inputted thereto; and a word-line decoder selecting a word line of said hidden memory block by boosting a word line of an adjacent memory block included in the primary memory area in response to the signal, said word-line decoder being included in said adjacent memory block, wherein the second data is read from said hidden memory block when said column decoder and said word-line decoder select the column corresponding to said hidden memory block and the word line of said hidden memory block respectively.

Claim 3

The semiconductor memory device as claimed in claim 1 , wherein said adjacent memory block includes a power source used for operating the word line of said adjacent memory block, said power source being used for selecting the word line of said hidden memory block.

Claim 4

The semiconductor memory device as claimed in claim 1 , wherein said plurality of memory blocks are arranged in a matrix structure, wherein the secondary memory area is provided in an empty space in said matrix structure.

Claim 5

A semiconductor memory device from which data is read by use of a segmental word line method, said semiconductor memory device comprising: a primary memory area including a plurality of memory blocks arranged in rows and columns, said plurality of memory blocks including a predetermined memory block; a secondary memory area including a hidden memory block situated in the same column as said predetermined memory block; a decision circuit selecting one of a first mode for reading first data from the primary memory area and a second mode for reading second data from the secondary memory area, said decision circuit outputting a signal when the second mode and an address of said predetermined memory block are specified; a column decoder selecting a column corresponding to a column address inputted thereto; a global-word-line decoder selecting a global word line of a row corresponding to a first row address when receiving the signal and the first row address, said global word line being connected to said hidden memory block and an adjacent memory block included in the primary memory area; and a local-word-line decoder selecting said hidden memory block by boosting a word line of said hidden memory block when receiving the signal and a second row address corresponding to the word line of said hidden memory block, wherein the second data is read from said hidden memory block when said global-word-line decoder, said local-word-line decoder and said column decoder select the global word line, the word line of said hidden memory block and the column corresponding to said hidden memory block respectively.

Claim 6

A semiconductor memory device from which data is read by use of a segmental word line method, said semiconductor memory device comprising: a primary memory area including a plurality of memory blocks arranged in rows and columns, said plurality of memory blocks including a predetermined memory block; a secondary memory area including a hidden memory block situated in the same column as said predetermined memory block; a decision circuit selecting one of a first mode for reading first data from the primary memory area and a second mode for reading second data from the secondary memory area, said decision circuit outputting a signal when the second mode and an address of said predetermined memory block are specified; a column decoder selecting a column corresponding to a column address inputted thereto; a global-word-line decoder selecting a global word line of a row corresponding to a first row address when receiving the signal and the first row address, said global word line being connected to said hidden memory block and an adjacent memory block included in the primary memory area; and a local-word-line decoder selecting said hidden memory block by boosting a word line of said hidden memory block when receiving the signal and a second row address corresponding to the word line of said hidden memory block, wherein the second data is read from said hidden memory block when said global-word-line decoder, said local-word-line decoder and said column decoder select the global word line, the word line of said hidden memory block and the column corresponding to said hidden memory block respectively.

Claim 7

The semiconductor memory device as claimed in claim 4 , wherein said adjacent memory block includes a power source used for operating a word line of said adjacent memory block, said power source being used for selecting the word line of said hidden memory block.

Claim 8

The semiconductor memory device as claimed in claim 4 , wherein said plurality of memory blocks are arranged in a matrix structure in the primary memory area, wherein the secondary memory area is provided in an empty space in said matrix structure.