Patent US6462979B2 successfully refreshed from Google Patents.
US6462979B2
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Integrated memory having memory cells with magnetoresistive storage effect
Assignee: Infineon Technologies AG
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Filing: 2001-03-05
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Granted: 2002-10-08
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Expires: 2021-03-05
Abstract
Abstract The integrated memory has memory cells with a magnetoresistive storage effect in a memory cell array in the form of a matrix. The memory cells are each connected between one of the column lines and one of the row lines. The column lines are each connected to a read amplifier for reading a data signal from a memory cell. The read amplifier has an operational amplifier with feedback, and a first control input connected to one of the column lines. A capacitor is connected between a second control input of the operational amplifier and a terminal for a supply potential and is used to compensate for any offset voltage at the control inputs of the operational amplifier. This allows a data signal which is to be read from one of the memory cells to be detected comparatively reliably.
Inventors
- 👤 Till Schlösser
- 👤 Roland Thewes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 01:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15; G11C11/16; G11C11/165; G11C11/1673
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
116 words
An integrated memory, comprising: a memory cell array in form of a matrix having column lines and row lines; a plurality of memory cells with a magnetoresistive storage effect each connected between one of said column lines and one of said row lines; read amplifiers respectively connected to each said column line for reading a data signal from a corresponding said memory cell; said read amplifier having an operational amplifier with a feedback path, and outputting a read signal, said operational amplifier having a first control input connected to one of said column lines and a second control input; and a capacitor connected between said second control input of said operational amplifier and a supply potential.
Claim 2
Dependent Claim
116 words
An integrated memory, comprising: a memory cell array in form of a matrix having column lines and row lines; a plurality of memory cells with a magnetoresistive storage effect each connected between one of said column lines and one of said row lines; read amplifiers respectively connected to each said column line for reading a data signal from a corresponding said memory cell; said read amplifier having an operational amplifier with a feedback path, and outputting a read signal, said operational amplifier having a first control input connected to one of said column lines and a second control input; and a capacitor connected between said second control input of said operational amplifier and a supply potential.
Claim 3
Dependent Claim
56 words
The integrated memory according to claim 1 , which further comprises: a first switch connected between said first control input and a terminal for the supply potential; a second switch connected in said feedback path of said operational amplifier; and a third switch connected between an output of said operational amplifier and said second control input.
Claim 4
Dependent Claim
34 words
The integrated memory according to claim 2 , wherein said operational amplifier is an inverting amplifier, and an inversion circuit is connected between said output and said second control input of said operational amplifier.
Claim 5
Dependent Claim
21 words
The integrated memory according to claim 1 , which comprises a resistor connected in said feedback path of said operational amplifier.
Claim 6
Dependent Claim
22 words
The integrated memory according to claim 1 , which comprises a further capacitor connected in said feedback path of said operational amplifier.
Claim 7
Dependent Claim
27 words
The integrated memory according to claim 5 , which comprises a switch connected in parallel with said further capacitor in said feedback path of said operational amplifier.
References Cited (Backward Citations)
US4439693A
Cited
US4695971A
Cited
US4922126A
Cited
US4829476A
Cited
US5282104A
Cited
WO1999014760A1
Cited
US6351408B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-07 | 2006-04-08 | 2006-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-07 | 2010-04-08 | 2010-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-07 | 2014-04-08 | 2014-10-08 | $7700.00 | Window Closed / Lapsed |