US6486065B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming nonvolatile memory device utilizing a hard mask
Assignee: SanDisk Technologies LLC
•
Filing: 2000-12-22
•
Granted: 2002-11-26
•
Expires: 2020-12-22
Abstract
Abstract The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features. The gap between the features is filled with the dielectric material which is softer than the masking layer with respect to a planarization
Inventors
- 👤 Michael A. Vyvoda
- 👤 N. Johan Knall
- 👤 James M. Cleeves
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:13
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10B; H10B20/00; H10B20/20; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
78 words
A method of fabricating a device comprising: forming a semiconductor layer having an upper surface; forming a masking layer over said semiconductor layer; patterning the masking layer; etching at least the semiconductor layer in alignment with the patterned masking layer to define array features, the features having an upper surface; filling between the features with a dielectric material which is softer than the masking layer; and planarizing the dielectric material with the masking layer acting as the stop.
Claim 2
Independent Claim
78 words
A method of fabricating a device comprising: forming a semiconductor layer having an upper surface; forming a masking layer over said semiconductor layer; patterning the masking layer; etching at least the semiconductor layer in alignment with the patterned masking layer to define array features, the features having an upper surface; filling between the features with a dielectric material which is softer than the masking layer; and planarizing the dielectric material with the masking layer acting as the stop.
Claim 3
Independent Claim
96 words
A method for fabricating a three-dimensional array comprising: forming a silicon layer having an upper surface; forming a masking layer over the silicon layer; patterning the masking layer; etching at least the silicon layer in alignment with the patterned masking layer to define memory array features, the features having an upper surface; filling between the features with a dielectric material which is softer than the masking layer; planarizing the dielectric material with the masking layer acting as a stop; removing the patterned masking layer; and forming an antifuse layer on the upper surface of the features.
Claim 4
Independent Claim
96 words
A method for fabricating a three-dimensional array comprising: forming a silicon layer having an upper surface; forming a masking layer over the silicon layer; patterning the masking layer; etching at least the silicon layer in alignment with the patterned masking layer to define memory array features, the features having an upper surface; filling between the features with a dielectric material which is softer than the masking layer; planarizing the dielectric material with the masking layer acting as a stop; removing the patterned masking layer; and forming an antifuse layer on the upper surface of the features.
Claim 5
Dependent Claim
23 words
The method defined by claim 2 wherein the antifuse layer is formed by a blanket deposition covering the features and the dielectric material.
Claim 6
Dependent Claim
13 words
The method defined by claim 2 wherein the antifuse layer is silicon dioxide.
Claim 7
Dependent Claim
19 words
The method defined by claim 2 wherein the silicon layer is formed by an annealing an amorphous silicon layer.
Claim 8
Dependent Claim
15 words
The method defined by claim 4 wherein the silicon dioxide is deposited by chemical-vapor-deposition (CVD).
Claim 9
Dependent Claim
16 words
The method defined by claim 2 wherein the antifuse layer is grown from the silicon layer.
Claim 10
Dependent Claim
18 words
The method defined by claim 7 wherein the grown silicon dioxide layer is grown in a steam atmosphere.
Claim 11
Dependent Claim
13 words
The method defined by claim 2 wherein the masking layer comprises silicon nitride.
Claim 12
Dependent Claim
13 words
The method defined by claim 9 wherein the dielectric material is silicon dioxide.
Claim 13
Dependent Claim
12 words
The method defined by claim 10 wherein the planarization comprises chemical-mechanical polishing.
Claim 14
Dependent Claim
14 words
The method defined by claim 11 wherein the silicon layer is a polysilicon layer.
Claim 15
Dependent Claim
14 words
The method defined by claim 11 wherein the polysilicon layer is a doped layer.
Claim 16
Independent Claim
100 words
A method for fabricating a three-dimensional memory array comprising: forming a polysilicon layer; forming a masking layer comprising silicon nitride over the polysilicon layer on an upper surface of the polysilicon layer; patterning the masking layer; etching at least the polysilicon layer in alignment with the patterned masking layer to define parallel, spaced-apart memory lines; filling spaces between the memory lines with a dielectric material which planarizes more readily than silicon nitride; planarizing the dielectric material with the silicon nitride layer acting as an etchant stop; removing the silicon nitride layer; forming a silicon dioxide layer over the polysilicon lines.
Claim 17
Independent Claim
100 words
A method for fabricating a three-dimensional memory array comprising: forming a polysilicon layer; forming a masking layer comprising silicon nitride over the polysilicon layer on an upper surface of the polysilicon layer; patterning the masking layer; etching at least the polysilicon layer in alignment with the patterned masking layer to define parallel, spaced-apart memory lines; filling spaces between the memory lines with a dielectric material which planarizes more readily than silicon nitride; planarizing the dielectric material with the silicon nitride layer acting as an etchant stop; removing the silicon nitride layer; forming a silicon dioxide layer over the polysilicon lines.
Claim 18
Dependent Claim
18 words
The method defined by claim 14 wherein the forming of the polysilicon comprises annealing an amorphous silicon layer.
Claim 19
Dependent Claim
20 words
The method defined by claim 14 wherein the silicon dioxide layer is a grown layer grown from the polysilicon lines.
Claim 20
Dependent Claim
17 words
The method defined by claim 16 wherein the silicon dioxide layer is grown in a steam atmosphere.
Claim 21
Dependent Claim
15 words
The method defined by claim 14 wherein the silicon dioxide layer is a deposited layer.
Claim 22
Dependent Claim
17 words
The method defined by claim 14 wherein the polysilicon lines are doped with a first conductivity-type dopant.
Claim 23
Dependent Claim
25 words
The method defined by claim 19 wherein another layer of polysilicon doped with a second conductivity type dopant is deposited over the silicon dioxide layer.
Claim 24
Dependent Claim
25 words
The method of claim 14 further comprising the step of forming a thin oxide on the polysilicon lines prior to forming said silicon nitride layer.
Claim 25
Independent Claim
172 words
A method of forming a nonvolatile memory array comprising: forming a first stack of films having a top silicon film of a first conductivity type; forming a masking layer on said top silicon film of said first stack of films; patterning said masking layer to form a patterned masking layer; etching said first stack of films in alignment with said patterned masking layer to form a plurality of spaced-apart lines from said first stack of films; depositing a dielectric material between said plurality of spaced-apart lines and on said patterned masking layer; planarizing said dielectric material with a chemical mechanical polishing process utilizing said masking layer as a polish stop; removing said patterned masking layer from said plurality of spaced-apart lines; forming an antifuse on said top silicon film of said plurality of spaced-apart lines; and forming a second stack of films having a lower silicon film of a second conductivity type opposite said first conductivity type on said antifuse on said top silicon film of said first plurality of rail stacks.
Claim 26
Independent Claim
172 words
A method of forming a nonvolatile memory array comprising: forming a first stack of films having a top silicon film of a first conductivity type; forming a masking layer on said top silicon film of said first stack of films; patterning said masking layer to form a patterned masking layer; etching said first stack of films in alignment with said patterned masking layer to form a plurality of spaced-apart lines from said first stack of films; depositing a dielectric material between said plurality of spaced-apart lines and on said patterned masking layer; planarizing said dielectric material with a chemical mechanical polishing process utilizing said masking layer as a polish stop; removing said patterned masking layer from said plurality of spaced-apart lines; forming an antifuse on said top silicon film of said plurality of spaced-apart lines; and forming a second stack of films having a lower silicon film of a second conductivity type opposite said first conductivity type on said antifuse on said top silicon film of said first plurality of rail stacks.
Claim 27
Independent Claim
184 words
A method of forming a memory comprising: forming a first stack of films having a top silicon film; forming a hard mask layer on said silicon top film; patterning said hard mask layer into a patterned hard mask having a plurality of spaced-apart lines; etching said first stack of films in alignment with said patterned hard mask to form a plurality of spaced-apart lines from said first stack of films; depositing a dielectric between said plurality of spaced-apart lines of said first film stack and onto said hard mask; planarizing said dielectric utilizing said hard mask as a planarization stop; removing said hard mask; depositing a conductive film over said top silicon film of said plurality of spaced-apart lines and over said planarized dielectric; patterning said conductive film into a plurality of conductive lines which run orthogonal to said first plurality of lines formed in said first stack of films; and etching said plurality of spaced-apart lines of said first stack of films in alignment with said conductive lines to form a plurality of pillars from said plurality of spaced-apart first stack of films.
Claim 28
Independent Claim
184 words
A method of forming a memory comprising: forming a first stack of films having a top silicon film; forming a hard mask layer on said silicon top film; patterning said hard mask layer into a patterned hard mask having a plurality of spaced-apart lines; etching said first stack of films in alignment with said patterned hard mask to form a plurality of spaced-apart lines from said first stack of films; depositing a dielectric between said plurality of spaced-apart lines of said first film stack and onto said hard mask; planarizing said dielectric utilizing said hard mask as a planarization stop; removing said hard mask; depositing a conductive film over said top silicon film of said plurality of spaced-apart lines and over said planarized dielectric; patterning said conductive film into a plurality of conductive lines which run orthogonal to said first plurality of lines formed in said first stack of films; and etching said plurality of spaced-apart lines of said first stack of films in alignment with said conductive lines to form a plurality of pillars from said plurality of spaced-apart first stack of films.
Claim 29
Independent Claim
189 words
A method of forming a memory comprising: forming a first stack of films having a top silicon film; forming a conductive hard mask layer on said silicon top film; patterning said conductive hard mask into a patterned conductive hard mask having a plurality of spaced-apart lines; etching said first stack of films in alignment with said patterned conductive hard mask to form a plurality of spaced-apart lines from said first stack of film; depositing a dielectric between said plurality of spaced-apart lines of said first film stack and onto said conductive hard mask; planarizing said dielectric utilizing said conductive hard mask as a planarization stop; depositing a conductive film over and in direct contact with said patterned conductive hard mask on said plurality of spaced-apart lines; patterning said conductive film into a plurality of conductive lines with run orthogonal to said first plurality of lines formed in said first stack of films; and etching said plurality of spaced-apart lines of said first stack of films in alignment with said conductive lines to form a plurality of pillars from said plurality of spaced-apart lines of said first stack of films.
Claim 30
Independent Claim
189 words
A method of forming a memory comprising: forming a first stack of films having a top silicon film; forming a conductive hard mask layer on said silicon top film; patterning said conductive hard mask into a patterned conductive hard mask having a plurality of spaced-apart lines; etching said first stack of films in alignment with said patterned conductive hard mask to form a plurality of spaced-apart lines from said first stack of film; depositing a dielectric between said plurality of spaced-apart lines of said first film stack and onto said conductive hard mask; planarizing said dielectric utilizing said conductive hard mask as a planarization stop; depositing a conductive film over and in direct contact with said patterned conductive hard mask on said plurality of spaced-apart lines; patterning said conductive film into a plurality of conductive lines with run orthogonal to said first plurality of lines formed in said first stack of films; and etching said plurality of spaced-apart lines of said first stack of films in alignment with said conductive lines to form a plurality of pillars from said plurality of spaced-apart lines of said first stack of films.
References Cited (Backward Citations)
US4119995A
Cited
US4119995B1
Cited
US4099196A
Cited
EP0073486A2
Cited
US4489478A
Cited
US4500905A
Cited
US5306935A
Cited
EP0395886A2
Cited
US5835396A
Cited
US6258656B1
Cited
US6034882A
Cited
US6294460B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-25 | 2006-05-27 | 2006-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-25 | 2010-05-27 | 2010-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-25 | 2014-05-27 | 2014-11-26 | $7700.00 | Window Closed / Lapsed |