US6567287B2
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US
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Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
Assignee: SanDisk Technologies LLC
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Filing: 2001-06-29
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Granted: 2003-05-20
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Expires: 2021-06-29
Abstract
Abstract The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
Inventors
- 👤 Roy E. Scheuerlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:50
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C17/00; G11C17/14; G11C17/18; G11C5/00; G11C5/02; G11C5/025; G11C7/00; G11C7/06; G11C7/062; G11C7/067; G11C7/18; G11C8/08; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
73 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array, and wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array.
Claim 2
Dependent Claim
73 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array, and wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array.
Claim 3
Dependent Claim
30 words
The invention of claim 1 further comprising only one set of wordline drivers between adjacent row decoder circuits, whereby wordlines are continuous between memory arrays over adjacent row decoder circuits.
Claim 4
Dependent Claim
30 words
The invention of claim 1 further comprising two sets of wordline drivers between adjacent row decoder circuits, whereby wordlines are not continuous between memory arrays over adjacent row decoder circuits.
Claim 5
Dependent Claim
30 words
The invention of claim 1 further comprising only one set of bitline drivers between adjacent column decoder circuits, whereby bitlines are continuous between memory arrays over adjacent column decoder circuits.
Claim 6
Dependent Claim
31 words
The invention of claim 1 further comprising two sets of bitline drivers between adjacent column decoder circuits, whereby bitlines are not continuous between memory arrays over the adjacent column decoder circuits.
Claim 7
Dependent Claim
20 words
The invention of claim 1 , wherein wordlines in a memory array are interleaved from two sets of wordline drivers.
Claim 8
Dependent Claim
20 words
The invention of claim 1 , wherein bitlines in a memory array are interleaved from two sets of bitline drivers.
Claim 9
Dependent Claim
61 words
The invention of claim 1 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays, wherein wordlines in each memory array are interleaved from two sets of wordline drivers, wherein bitlines in each memory array are interleaved from two sets of bitline drivers, and wherein each memory array comprises a plurality of anti-fuse memory cells.
Claim 10
Dependent Claim
61 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both.
Claim 11
Dependent Claim
61 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both.
Claim 12
Dependent Claim
61 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit.
Claim 13
Dependent Claim
61 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit.
Claim 14
Dependent Claim
89 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays.
Claim 15
Dependent Claim
89 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays.
Claim 16
Dependent Claim
70 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides.
Claim 17
Dependent Claim
70 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides.
Claim 18
Dependent Claim
70 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides.
Claim 19
Dependent Claim
70 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides.
Claim 20
Dependent Claim
39 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising only one set of wordline drivers between adjacent row decoder circuits, whereby wordlines are continuous between memory arrays over adjacent row decoder circuits.
Claim 21
Dependent Claim
39 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising two sets of wordline drivers between adjacent row decoder circuits, whereby wordlines are not continuous between memory arrays over adjacent row decoder circuits.
Claim 22
Dependent Claim
39 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising only one set of bitline drivers between adjacent column decoder circuits, whereby bitlines are continuous between memory arrays over adjacent column decoder circuits.
Claim 23
Dependent Claim
40 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising two sets of bitline drivers between adjacent column decoder circuits, whereby bitlines are not continuous between memory arrays over the adjacent column decoder circuits.
Claim 24
Dependent Claim
29 words
The invention of claim 9 , 10 , 11 , 12 , or 13 , wherein wordlines in a memory array are interleaved from two sets of wordline drivers.
Claim 25
Dependent Claim
29 words
The invention of claim 9 , 10 , 11 , 12 , or 13 , wherein bitlines in a memory array are interleaved from two sets of bitline drivers.
Claim 26
Dependent Claim
28 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising at least one additional row decoder circuit not under a memory cell.
Claim 27
Dependent Claim
28 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising at least one additional column decoder circuit not under a memory cell.
Claim 28
Dependent Claim
49 words
The invention of claim 9 , 10 , 11 , 12 , or 13 , wherein at least one row decoder circuit comprises a plurality of wordline decoders, and wherein the plurality of wordline decoders are connected to a respective plurality of wordlines through a respective plurality of switches.
Claim 29
Dependent Claim
26 words
The invention of claim 9 , 10 , 11 , 12 , or 13 , wherein the plurality of memory arrays are fabricated above a substrate.
Claim 30
Dependent Claim
31 words
The invention of claim 9 , 10 , 11 , 12 , or 13 , further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays.
Claim 31
Dependent Claim
25 words
The invention of claim 9 , 10 , 11 , 12 , or 13 , wherein the plurality of memory arrays comprise write-once memory cells.
Claim 32
Dependent Claim
70 words
The invention of claim 9 , 10 , 11 , 12 , or 13 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays, wherein wordlines in each memory array are interleaved from two sets of wordline drivers, wherein bitlines in each memory array are interleaved from two sets of bitline drivers, and wherein each memory array comprises a plurality of anti-fuse memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-19 | 2006-11-18 | 2007-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-19 | 2010-11-18 | 2011-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-19 | 2014-11-18 | 2015-05-20 | $7700.00 | Window Closed / Lapsed |