US6567312B1
Expired / Lapsed
US
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Non-volatile semiconductor memory device having a charge storing insulation film and data holding method therefor
Assignee: Cypress Semiconductor Corp
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Filing: 2000-10-13
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Granted: 2003-05-20
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Expires: 2020-10-13
Abstract
Abstract In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.
Inventors
- 👤 Satoshi Torii
- 👤 Hideyuki Kojima
- 👤 Hiroshi Mawatari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:53
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
118 words
A non-volatile semiconductor memory device (EEPROM) including a memory cell array arranging a plurality of memory cells; enabling electrical programming through the transfer, of charges between a charge trap layer and a semiconductor substrate, in the form of a matrix, each of such cells is formed by sequentially laminating, on said semiconductor substrate, a first gate oxide film, said charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode, wherein after data is written to said memory cell, post-write operation is conducted so as to add pulse bring shorter than a pulse for erase operation.
Claim 2
Dependent Claim
118 words
A non-volatile semiconductor memory device (EEPROM) including a memory cell array arranging a plurality of memory cells; enabling electrical programming through the transfer, of charges between a charge trap layer and a semiconductor substrate, in the form of a matrix, each of such cells is formed by sequentially laminating, on said semiconductor substrate, a first gate oxide film, said charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode, wherein after data is written to said memory cell, post-write operation is conducted so as to add pulse bring shorter than a pulse for erase operation.
Claim 3
Dependent Claim
113 words
The non-volatile semiconductor memory device as claimed in claim 1 , comprising, under the condition of 0≦|Vws|≦|Vwe|, 0≦|Vbs|≦|Vbe|, ts≦te; means for writing data to said memory cells by applying voltages Vwp to said gate electrode and Vdp to the drain of said memory cells; means for erasing data from said memory cells by applying for te seconds the erase voltages Vwe to said gate insulation film and Vbe to the source and drain of said memory cells; and means for removing a part of the electrons by applying for ts seconds the voltage Vwe to said gate insulation film and the voltage Vbs to said source and drain after said data writing operation.
Claim 4
Dependent Claim
25 words
The non-volatile semiconductor memory device as claimed in claim 2 , wherein a part of the electrons is removed under the voltage condition of Vbs=Vdp.
Claim 5
Dependent Claim
60 words
A non-volatile semiconductor memory deice as claimed in any one of claims 1 to 3 , wherein after data is written to said memory cell array on the occasion of executing the data verify write operation, a part of said electrons is removed and a verify operation is performed and such operations are repeated until the data is written sufficiently.
Claim 6
Dependent Claim
148 words
A data holding method of a non-volatile semiconductor memory device for applying for a short period of time, a voltage equal to the voltage required to erase data stored in a memory cell, in order to add a pulse for post-write operation so as to be shorter than a pulse for erase operation to the non-volatile semiconductor memory device (EEPROM) including a memory cell array comprising the steps of: arranging a plurality of memory cells, enabling electrical programming through the transfer of charge between a charge trap layer and a semiconductor substrate in form of matrix, each of such cells is formed by sequentially laminating, on said semiconductor substrate, a first gate oxide film, said charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode.
Claim 7
Dependent Claim
148 words
A data holding method of a non-volatile semiconductor memory device for applying for a short period of time, a voltage equal to the voltage required to erase data stored in a memory cell, in order to add a pulse for post-write operation so as to be shorter than a pulse for erase operation to the non-volatile semiconductor memory device (EEPROM) including a memory cell array comprising the steps of: arranging a plurality of memory cells, enabling electrical programming through the transfer of charge between a charge trap layer and a semiconductor substrate in form of matrix, each of such cells is formed by sequentially laminating, on said semiconductor substrate, a first gate oxide film, said charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode.
Claim 8
Dependent Claim
117 words
A data holding method of the non-volatile semiconductor memory device as claimed in claim 5 , further comprising the steps of, under the condition of 0≦|Vws|≦|Vwe| and 0≦|Vbs|≦|Vbe|, ts≦te: writing data to said memory cells by applying voltages Vwp to said gate electrode and Vdp to the drain of said memory cells; erasing data from said memory cells by applying for te seconds the erase voltages Vwe to said gate insulation film and Vbe to the source and drain of said memory cells; and removing a part of the electrons by applying for ts seconds the voltage Vwe to said gate insulation film an the voltage Vbs to said source and drain after said data writing operation.
Claim 9
Dependent Claim
29 words
The data holding method of the non-volatile semiconductor memory device as claimed in claim 6 , wherein a part of electrons is removed under the voltage condition of Vbs=Vdp.
Claim 10
Dependent Claim
64 words
A data holding method of the non-volatile semiconductor memory device as claimed in any one of claims 5 to 7 , wherein after data is written to said memory cell array on the occasion of executing the data verify write operation, a part of said electrons is removed and verify operation is performed and such operations are repeated until that data is written sufficiently.
Claim 11
Dependent Claim
59 words
An EEPROM, employing a memory cell having a charge trap layer capable of capturing charges easier than silicon oxide film; and being capable of writing data through an action of injecting charges into said charge trap layer, followed by an action of adding a pulse for post-write operation so as to be shorter than a pulse for erase operation.
Claim 12
Dependent Claim
59 words
An EEPROM, employing a memory cell having a charge trap layer capable of capturing charges easier than silicon oxide film; and being capable of writing data through an action of injecting charges into said charge trap layer, followed by an action of adding a pulse for post-write operation so as to be shorter than a pulse for erase operation.
Claim 13
Dependent Claim
19 words
The EEPROM as claimed in claim 9 , wherein said charge trap layer is comprised from silicon and nitrogen.
Claim 14
Dependent Claim
19 words
The EEPROM as claimed in claim 9 , wherein said charge trap layer is comprised from silicon nitride film.
Claim 15
Dependent Claim
23 words
The EEPROM as claimed in claim 9 , wherein said charge trap layer is comprised from a stacked film of silicon oxide/silicon nitride.
Claim 16
Dependent Claim
23 words
The EEPROM as claimed in claim 9 , wherein said charge trap layer is comprised from a staked film of Silicon Oxide/Aluminum Oxide.
Claim 17
Dependent Claim
23 words
The EEPROM as claimed in claim 9 , wherein said charge trap layer is comprised from a stacked film of Silicon Oxide/Tantalum Oxide.
Claim 18
Dependent Claim
26 words
The EEPROM as claimed in any one of claims 12 through 14 , wherein said charge trap layer further comprising a Silicon Oxide at its uppermost.
Claim 19
Dependent Claim
43 words
The EEPROM as claimed in claim 9 , wherein said action of partially drawing said charge from said charge trap layer is performed through an action of adding a shortened pulse of the same potentials as data erase operation of said memory cell.
Claim 20
Dependent Claim
33 words
The EEPROM as claimed in claim 9 , wherein said action of partially drawing said charge from said charge trap layer is automatically preceded without any external pulses after said data write operation.
Claim 21
Dependent Claim
34 words
The EEPROM as claimed in claim 9 , wherein said action of partially drawing said charge from said charge trap layer is automatically preceded by a predetermined time delay after said data write operation.
Claim 22
Dependent Claim
43 words
The EEPROM as claimed in claim 9 , wherein said action of partially drawing said charge from said charge trap layer is performed by a pulse, generated in a pulse generation circuit; and said pulse generation circuit is activated by inputting external signal.
Claim 23
Dependent Claim
35 words
The EEPROM as claimed in claim 9 , wherein said action of partially drawing said charge from said charge trap layer is performed by a pulse, externally generated and inputted before said data write operation.
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