US6583479B1
Expired / Lapsed
US
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Sidewall NROM and method of manufacture thereof for non-volatile memory cells
Assignee: Monterey Research LLC
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Filing: 2000-10-16
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Granted: 2003-06-24
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Expires: 2020-10-16
Abstract
Abstract An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.
Inventors
- 👤 Richard M. Fastow
- 👤 Shane C. Hollmer
- 👤 Pau-Ling Chen
- 👤 Michael Van Buskirk
- 👤 Masaaki Higashitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 01:32
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0413; H10D30/60; H10D30/68; H10D30/687; H10D30/6891; H10D30/6893; H10D30/6894; H10D30/69; H10D30/691; H10D64/00; H10D64/01; H10D64/031; H10D64/037; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; G11C16/0466; G11C16/0475; G11C16/0491; G11C2216/00; G11C2216/02; G11C2216/06; H10D30/0411; H10D64/035
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
117 words
A non-volatile read only memory transistor comprising: a channel region having a first end coupled with a source and a second end coupled with a drain; a gate comprising a wordline layer formed in a trench without completely filling said trench; said source having a first surface located in a first plane and said drain having a second surface located in a second plane, said second plane being oriented substantially parallel to and non-coplanar with said first plane; and wherein said channel region is located in a third plane, said third plane being oriented substantially perpendicular to and non-coplanar with said first and second planes, and wherein said drain overlaps at least a portion of said source.
Claim 2
Dependent Claim
117 words
A non-volatile read only memory transistor comprising: a channel region having a first end coupled with a source and a second end coupled with a drain; a gate comprising a wordline layer formed in a trench without completely filling said trench; said source having a first surface located in a first plane and said drain having a second surface located in a second plane, said second plane being oriented substantially parallel to and non-coplanar with said first plane; and wherein said channel region is located in a third plane, said third plane being oriented substantially perpendicular to and non-coplanar with said first and second planes, and wherein said drain overlaps at least a portion of said source.
Claim 3
Dependent Claim
18 words
The non-volatile read only memory transistor of claim 1 further comprising an Oxide-Nitride-Oxide (“ONO”) layer overlaying said channel.
Claim 4
Dependent Claim
116 words
An electronic device comprising: one or more non-volatile read only memory transistors, said one or more non-volatile read only memory transistors each comprising: a channel having a first end comprising a source and a second end comprising a drain; a gate comprising a wordline layer formed in a trench without completely filling said trench; said source being located in a first plane and said drain located in a second plane, said second plane being oriented substantially parallel to said first plane; and wherein said channel is located in a third plane, said third plane being oriented substantially perpendicular to said first and second planes, and wherein said drain overlaps at least a portion of said source.
Claim 5
Dependent Claim
116 words
An electronic device comprising: one or more non-volatile read only memory transistors, said one or more non-volatile read only memory transistors each comprising: a channel having a first end comprising a source and a second end comprising a drain; a gate comprising a wordline layer formed in a trench without completely filling said trench; said source being located in a first plane and said drain located in a second plane, said second plane being oriented substantially parallel to said first plane; and wherein said channel is located in a third plane, said third plane being oriented substantially perpendicular to said first and second planes, and wherein said drain overlaps at least a portion of said source.
Claim 6
Dependent Claim
25 words
The electronic device of claim 3 , wherein said one or more non-volatile read only memory transistors further comprise an ONO layer overlaying said channel.
Claim 7
Dependent Claim
180 words
An electronic device comprising: a substrate comprising one or more trenches formed in said substrate, each of said one or more trenches having first and second top portions, a bottom portion oriented substantially parallel to said first and second top portions, a first wall extending between said first top portion and said bottom portion substantially perpendicularly to said bottom and said first top portion and a second wall extending substantially perpendicularly from said second top portion to said bottom portion, said first wall being substantially parallel to said second wall; a first non-volatile read only memory transistor, comprising: a first channel having a first end comprising a first source and a second end comprising a first drain; a first gate comprising a wordline layer formed in one of said trenches without completely filling said trench; said first drain being located in said first top portion and said first source being located in said bottom portion; and wherein said first channel is located in said first wall, and wherein said first drain overlaps at least a portion of said first source.
Claim 8
Dependent Claim
180 words
An electronic device comprising: a substrate comprising one or more trenches formed in said substrate, each of said one or more trenches having first and second top portions, a bottom portion oriented substantially parallel to said first and second top portions, a first wall extending between said first top portion and said bottom portion substantially perpendicularly to said bottom and said first top portion and a second wall extending substantially perpendicularly from said second top portion to said bottom portion, said first wall being substantially parallel to said second wall; a first non-volatile read only memory transistor, comprising: a first channel having a first end comprising a first source and a second end comprising a first drain; a first gate comprising a wordline layer formed in one of said trenches without completely filling said trench; said first drain being located in said first top portion and said first source being located in said bottom portion; and wherein said first channel is located in said first wall, and wherein said first drain overlaps at least a portion of said first source.
Claim 9
Dependent Claim
27 words
The electronic device of claim 5 , wherein said at least one non-volatile read only memory transistor further comprises an Oxide-Nitride-Oxide (“ONO”) layer located overlaying said channel.
Claim 10
Dependent Claim
30 words
The electronic device of claim 5 , wherein said substrate is characterized by a substantially flat surface and wherein said one or more trenches extend a length of said surface.
Claim 11
Dependent Claim
48 words
The electronic device of claim 5 , wherein said one or more trenches are each characterized by a depth between said first and second top portions and said bottom portion and further wherein said channel comprises a channel length, said channel length being a function of said depth.
Claim 12
Dependent Claim
66 words
The electronic device of claim 5 , further comprising a second non-volatile read only memory transistor, comprising: a second channel having a third end comprising a second source and a fourth end comprising a second drain; said second drain being located in said second top portion and second source being located in said bottom portion; and wherein said second channel is located in said second wall.
Claim 13
Dependent Claim
18 words
The electronic device of claim 9 , wherein said first source is the same as said second source.
Claim 14
Dependent Claim
97 words
A non-volatile read only memory transistor comprising: a substrate having a substantially planar surface and a trench; a gate comprising a wordline layer formed in said trench without completely filling said trench; a source region fabricated in said substrate; a drain region fabricated in said substrate; and a channel region fabricated in said substrate and extending between and connecting said source region and said drain region; and wherein said channel region is out of plane of said source region and said drain region, and wherein said drain region overlaps at least a portion of said source region.
Claim 15
Dependent Claim
97 words
A non-volatile read only memory transistor comprising: a substrate having a substantially planar surface and a trench; a gate comprising a wordline layer formed in said trench without completely filling said trench; a source region fabricated in said substrate; a drain region fabricated in said substrate; and a channel region fabricated in said substrate and extending between and connecting said source region and said drain region; and wherein said channel region is out of plane of said source region and said drain region, and wherein said drain region overlaps at least a portion of said source region.
Claim 16
Dependent Claim
76 words
The non-volatile read only memory transistor of claim 11 , further comprising: a trench fabricated in said substrate having a bottom portion substantially parallel to said planar surface and a side portion substantially perpendicular to said planar surface and said bottom portion; wherein said drain region is fabricated substantially adjacent to said trench in said planar surface and said source region is fabricated in said bottom portion, said channel region is fabricated in said side portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-23 | 2006-12-23 | 2007-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-23 | 2010-12-23 | 2011-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-23 | 2014-12-23 | 2015-06-24 | $7700.00 | Window Closed / Lapsed |