US6618292B2
Expired / Lapsed
US
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Semiconductor memory device and method of operating the same
Assignee: Toshiba Corp
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Filing: 2001-11-13
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Granted: 2003-09-09
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Expires: 2021-11-13
Abstract
Abstract In a semiconductor memory device the potential of a semiconductor substrate and that of all of a plurality of word lines are increased to an erase voltage by means of a boosting circuit, and subsequently the potential of the word line selected by a word line selection circuit is decreased, when data of a memory cell is erased.
Inventors
- 👤 Koji Sakui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:11
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C16/06; G11C16/08; G11C16/10; G11C16/14; G11C16/16; G11C2216/00; G11C2216/12; G11C2216/18
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
142 words
A semiconductor memory device comprising: a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines; a word line selection circuit which selects one of said plurality of word lines; a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines; and a control circuit which controls said boosting circuit, said control circuit increasing the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit and subsequently decreasing the potential of the word line selected by said word line selection circuit.
Claim 2
Dependent Claim
142 words
A semiconductor memory device comprising: a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines; a word line selection circuit which selects one of said plurality of word lines; a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines; and a control circuit which controls said boosting circuit, said control circuit increasing the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit and subsequently decreasing the potential of the word line selected by said word line selection circuit.
Claim 3
Dependent Claim
67 words
The device according to claim 1 , wherein each of said plurality of memory cell units comprises columns of memory cells formed by connecting memory cells in series, bit line side selection gates connected in series respectively between said columns of memory cells and the bit lines and source line side selection gates connected in series respectively between said columns of memory cells and the source lines.
Claim 4
Dependent Claim
40 words
The device according to claim 1 , wherein said memory cell array comprises a plurality of cell blocks, each of said plurality of cell brocks having a predetermined number of memory cell units of said plurality of memory cell units.
Claim 5
Dependent Claim
48 words
The device according to claim 1 , wherein said memory cell array comprises a plurality of cell blocks, said word line selection circuit being selected of said plurality of word lines on the basis of a unit of cell block when data of a memory cell is erased.
Claim 6
Dependent Claim
82 words
The device according to claim 1 , wherein said semiconductor substrate comprises a semiconductor impurity layer of the first conductivity type, a first well region of a semiconductor impurity layer of the second conductivity type being formed on the surface of said semiconductor substrate, and a second well region of semiconductor impurity layer of the first conductivity type being formed on the surface of said first well region, said memory cell array being formed on the surface of said second well region.
Claim 7
Dependent Claim
237 words
A semiconductor memory device comprising: a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of NAND type memory cell units in array, each of said plurality of NAND type memory cell units being formed by connecting a plurality of rewritable nonvolatile memory cells in series, said plurality of rewritable nonvolatile memory cells being connected respectively to a plurality of word lines, each of said plurality of NAND type memory cell units being connected at an end thereof to a plurality of bit lines and at the other end thereof to a common source line; a word line selection circuit which selects one of said plurality of word lines; a bit line selection circuit which selects one of said plurality of bit lines; a sense amplifier circuit connected to said plurality of bit lines; said sense amplifier circuit having a latch function; a transfer gate being arranged between said sense amplifier circuit and said plurality of bit lines; a boosting circuit which boosts the potentials of said semiconductor substrate and said plurality of word lines; and a control circuit which controls said boosting circuit, said control circuit increasing the potentials of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit and subsequently decreasing the potential of the word line selected by said word line selection circuit.
Claim 8
Dependent Claim
237 words
A semiconductor memory device comprising: a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of NAND type memory cell units in array, each of said plurality of NAND type memory cell units being formed by connecting a plurality of rewritable nonvolatile memory cells in series, said plurality of rewritable nonvolatile memory cells being connected respectively to a plurality of word lines, each of said plurality of NAND type memory cell units being connected at an end thereof to a plurality of bit lines and at the other end thereof to a common source line; a word line selection circuit which selects one of said plurality of word lines; a bit line selection circuit which selects one of said plurality of bit lines; a sense amplifier circuit connected to said plurality of bit lines; said sense amplifier circuit having a latch function; a transfer gate being arranged between said sense amplifier circuit and said plurality of bit lines; a boosting circuit which boosts the potentials of said semiconductor substrate and said plurality of word lines; and a control circuit which controls said boosting circuit, said control circuit increasing the potentials of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit and subsequently decreasing the potential of the word line selected by said word line selection circuit.
Claim 9
Dependent Claim
76 words
The device according to claim 6 , wherein each of said plurality of NAND type memory cell units comprises columns of nonvolatile memory cells formed by connecting nonvolatile memory cells in series, bit line side selection gates connected respectively in series between said columns of nonvolatile memory cells and said plurality of bit lines and source line side selection gates connected respectively in series between said columns of nonvolatile memory cells and said common source lines.
Claim 10
Dependent Claim
44 words
The device according to claim 6 , wherein said memory cell array comprises a plurality of cell blocks, each of said plurality of cell blocks having a predetermined number of NAND type memory cell units of said plurality of NAND type memory cell units.
Claim 11
Dependent Claim
49 words
The device according to claim 6 , wherein said memory cell array comprises a plurality of cell blocks, said word line selection circuit being selected of said plurality of word lines on the basis of a unit of cell block when data of a nonvolatile memory cell is erased.
Claim 12
Dependent Claim
82 words
The device according to claim 6 , wherein said semiconductor substrate comprises a semiconductor impurity layer of the first conductivity type, a first well region of a semiconductor impurity layer of the second conductivity type being formed on the surface of said semiconductor substrate, and a second well region of semiconductor impurity layer of the first conductivity type being formed on the surface of said first well region, said memory cell array being formed on the surface of said second well region.
Claim 13
Independent Claim
157 words
A method of operating a semiconductor memory device, said semiconductor memory device including a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines, a word line selection circuit which selects one of said plurality of word lines, a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines, and a control circuit which controls said boosting circuit; said method comprising increasing the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and subsequently decreasing the potential of the word line selected by said word line selection circuit under the control of said control circuit.
Claim 14
Independent Claim
157 words
A method of operating a semiconductor memory device, said semiconductor memory device including a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines, a word line selection circuit which selects one of said plurality of word lines, a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines, and a control circuit which controls said boosting circuit; said method comprising increasing the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and subsequently decreasing the potential of the word line selected by said word line selection circuit under the control of said control circuit.
Claim 15
Dependent Claim
51 words
The method according to claim 11 , wherein the erase voltage from said boosting circuit is applied to all the word lines selected by said word line selection circuit out of said plurality of word lines under the control of said control circuit when data of a memory cell is erased.
Claim 16
Dependent Claim
40 words
The method according to claim 11 , wherein the erase voltage from said boosting circuit is applied to the well regions in said semiconductor substrate under the control of said control circuit when data of a memory cell is erased.
Claim 17
Dependent Claim
74 words
The method according to claim 11 , wherein the erase voltage from said boosting circuit is applied to all the bit line side selection gates connected respectively between said plurality of memory cell units and the bit lines and all the source line side selection gates connected respectively between said plurality of memory cell units and the source lines under the control of said control circuit when data of a memory cell is erased.
Claim 18
Dependent Claim
61 words
The method according to claim 11 , wherein only the potential of the word lines connected to the memory cells selected on the basis of a unit of cell block by ways said word line selection circuit which erases data is brought to the ground level under the control of said control circuit when data of a memory cell is erased.
Claim 19
Dependent Claim
155 words
The method according to claim 11 , wherein all the source line side selection gates in the cell block selected by said word line selection circuit are brought into an electrically conductive state, all the channel potentials of the columns of memory cells in said cell block are increased by the write prohibition voltage from the source lines, subsequently all said source line side selection gates in said cell block are made electrically non-conductive while the bit line side selection gates in said cell block are made electrically conductive according to the page data relating to the word lines connected to the memory cells to be used for writing data, and only the channel potential of the column of memory cells to be used for writing data is brought to the ground level by way of a sense amplifier circuit under the control of said control circuit when data is written into a memory cell.
Claim 20
Independent Claim
245 words
A method of operating a semiconductor memory device, said semiconductor memory device including a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of NAND type memory cell units in array, each of said plurality of NAND type memory cell units being formed by connecting a plurality of rewritable nonvolatile memory cells in series, said plurality of rewritable nonvolatile memory cells being connected respectively to a plurality of word lines, each of said plurality of NAND type memory cell units being connected at an end thereof to a plurality of bit lines and at the other end thereof to a common source line, a word line selection circuit which selects one of said plurality of word lines, a bit line selection circuit which selects one of said plurality of bit lines, a sense amplifier circuit connected to said plurality of bit lines, said sense amplifier circuit having a latch function, a transfer gate being arranged between said sense amplifier circuit and said plurality of bit lines, a boosting circuit which boosts the potentials of said semiconductor substrate and said plurality of word lines, and a control circuit which controls said boosting circuit; said method comprising increasing the potentials of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and subsequently decreasing the potential of the word line selected by said word line selection circuit.
Claim 21
Independent Claim
245 words
A method of operating a semiconductor memory device, said semiconductor memory device including a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of NAND type memory cell units in array, each of said plurality of NAND type memory cell units being formed by connecting a plurality of rewritable nonvolatile memory cells in series, said plurality of rewritable nonvolatile memory cells being connected respectively to a plurality of word lines, each of said plurality of NAND type memory cell units being connected at an end thereof to a plurality of bit lines and at the other end thereof to a common source line, a word line selection circuit which selects one of said plurality of word lines, a bit line selection circuit which selects one of said plurality of bit lines, a sense amplifier circuit connected to said plurality of bit lines, said sense amplifier circuit having a latch function, a transfer gate being arranged between said sense amplifier circuit and said plurality of bit lines, a boosting circuit which boosts the potentials of said semiconductor substrate and said plurality of word lines, and a control circuit which controls said boosting circuit; said method comprising increasing the potentials of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and subsequently decreasing the potential of the word line selected by said word line selection circuit.
Claim 22
Dependent Claim
52 words
The method according to claim 17 , wherein the erase voltage from said boosting circuit is applied to all the word lines selected by said word line selection circuit out of said plurality of word lines under the control of said control circuit when data of a nonvolatile memory cell is erased.
Claim 23
Dependent Claim
41 words
The method according to claim 17 , wherein the erase voltage from said boosting circuit is applied to the well regions in said semiconductor substrate under the control of said control circuit when data of a nonvolatile memory cell is erased.
Claim 24
Dependent Claim
82 words
The method according to claim 17 , wherein the erase voltage from said boosting circuit is applied to all the bit line side selection gates connected respectively between said plurality of NAND type memory cell units and said plurality of bit lines and all the source line side selection gates connected respectively between said plurality of NAND type memory cell units and said common source lines under the control of said control circuit when data of a nonvolatile memory cell is erased.
Claim 25
Dependent Claim
63 words
The method according to claim 17 , wherein only the potential of the word lines connected to the nonvolatile memory cells selected on the basis of a unit of cell block by ways said word line selection circuit which erases data is brought to the ground level under the control of said control circuit when data of a nonvolatile memory cell is erased.
Claim 26
Dependent Claim
158 words
The method according to claim 17 , wherein all the source line side selection gates in the cell block selected by said word line selection circuit are brought into an electrically conductive state, all the channel potentials of the columns of memory cells in said cell block are increased by the write prohibition voltage from said common source lines, subsequently all said source line side selection gates in said cell block are made electrically non-conductive while the bit line side selection gates in said cell block are made electrically conductive according to the page data relating to the word lines connected to the nonvolatile memory cells to be used for writing data, and only the channel potential of the column of memory cells to be used for writing data is brought to the ground level by way of a sense amplifier circuit under the control of said control circuit when data is written into a nonvolatile memory cell.
Claim 27
Dependent Claim
160 words
A semiconductor memory device comprising: a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines; a word line selection circuit which selects one of said plurality of word lines; a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines; and a control circuit which controls said boosting circuit, said control circuit being configured to increase the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and to subsequently decrease the potential of the word line selected by said word line selection circuit while maintaining the potential of the word lines other than the selected word line.
Claim 28
Dependent Claim
160 words
A semiconductor memory device comprising: a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines; a word line selection circuit which selects one of said plurality of word lines; a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines; and a control circuit which controls said boosting circuit, said control circuit being configured to increase the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and to subsequently decrease the potential of the word line selected by said word line selection circuit while maintaining the potential of the word lines other than the selected word line.
Claim 29
Dependent Claim
67 words
The device according to claim 23 , wherein each of said plurality of memory cell units comprises columns of memory cells formed by connecting memory cells in series, bit line side selection gates connected in series respectively between said columns of memory cells and the bit lines and source line side selection gates connected in series respectively between said columns of memory cells and the source lines.
Claim 30
Dependent Claim
40 words
The device according to claim 23 , wherein said memory cell array comprises a plurality of cell blocks, each of said plurality of cell blocks having a predetermined number of memory cell units of said plurality of memory cell units.
Claim 31
Dependent Claim
48 words
The device according to claim 23 , wherein said memory call array comprises a plurality of cell blocks, said word line selection circuit being selected of said plurality of word lines on the basis of a unit of cell block when data of a memory cell is erased.
Claim 32
Dependent Claim
95 words
The device according to claim 23 , wherein said semiconductor substrate comprises a semiconductor imurity layer of the first conductivity type, a first well region of a semiconductor impurity layer of the second conductivity type being formed on the surface of said semiconductor substrate, and a second well region of semiconductor impurity layer of the first conductivity type being formed on the surface of said first well region, said memory cell array being formed on the surface of said first well region, said memory cell array being formed on the surface of said well region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-09-08 | 2007-03-10 | 2007-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-08 | 2011-03-10 | 2011-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-08 | 2015-03-10 | 2015-09-09 | $7700.00 | Window Closed / Lapsed |