Patent US6632742B2 successfully refreshed from Google Patents.
US6632742B2
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Method for avoiding defects produced in the CMP process
Assignee: Promos Technologies Inc
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Filing: 2001-04-18
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Granted: 2003-10-14
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Expires: 2021-04-18
Abstract
Abstract A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.
Inventors
- 👤 Ming-Cheng Yang
- 👤 Jiun-Fang Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:08
CPC Classifications
H; H10; H10P; H10P52/00; H10P52/40; H10P52/403; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
A method for avoiding defects produced in The CMP process, comprising the steps of: (a) providing a semiconductor substrate which has a predetermined conductive wire area; (b) sequentially depositing a first dielectric layer and a second dielectric layer on the semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; (c) performing dry etching process to form a plurality of first holes on the predetermined conductive wire area, wherein each of the first holes passes through the second dielectric layer and the first dielectric layer until a first predetermined depth; (d) performing wet etching process to etch the first dielectric layer in each of the first holes until a second predetermined depth, and thereby the first holes passing through each other become a second hole on the predetermined conductive wire area; (e) forming a conductive layer to fill the second hole; and (f) performing the CMP process to level off the conductive layer and the second dielectric layer.
Claim 2
Independent Claim
170 words
A method for avoiding defects produced in The CMP process, comprising the steps of: (a) providing a semiconductor substrate which has a predetermined conductive wire area; (b) sequentially depositing a first dielectric layer and a second dielectric layer on the semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; (c) performing dry etching process to form a plurality of first holes on the predetermined conductive wire area, wherein each of the first holes passes through the second dielectric layer and the first dielectric layer until a first predetermined depth; (d) performing wet etching process to etch the first dielectric layer in each of the first holes until a second predetermined depth, and thereby the first holes passing through each other become a second hole on the predetermined conductive wire area; (e) forming a conductive layer to fill the second hole; and (f) performing the CMP process to level off the conductive layer and the second dielectric layer.
Claim 3
Dependent Claim
27 words
The method as claimed in claim 1 , wherein the wet-etching rate of the first dielectric layer to the second dielectric layer is not smaller than 3.
Claim 4
Dependent Claim
29 words
The method as claimed in claim 1 , wherein the first dielectric layer is made by borophosphosilicate glass (BPSG) and the second dielectric layer is made by silane oxide.
Claim 5
Dependent Claim
26 words
The method as claimed in claim 1 , wherein the first dielectric layer is made by oxide and the second dielectric layer is made by nitride.
Claim 6
Dependent Claim
26 words
The method as claimed in claim 1 , wherein the bottom diameter of the second hole is equal to the diameter of the predetermined conductive wire.
Claim 7
Dependent Claim
25 words
The method as claimed in claim 1 , further comprising the step of: (g) performing wet etching process to remove the exposed second dielectric layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-10-13 | 2007-04-14 | 2007-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-10-13 | 2011-04-14 | 2011-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-10-13 | 2015-04-14 | 2015-10-14 | $7700.00 | Window Closed / Lapsed |