US6689656B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory and the method for fabricating thereof
Assignee: DongbuAnam Semiconductor Inc
•
Filing: 2003-03-18
•
Granted: 2004-02-10
•
Expires: 2023-03-18
Abstract
Abstract The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interposed an insulation layer between therewith, thereby forming a trench capacitor at a region, which is used to be formed a transistor in the conventional art. Accordingly, when forming the trench capacitors, in which the numbers are the same as the conventional art, at the same silicon substrate area, a trench capacitor with large in diameter and shallow in depth can be formed, thereby performing a trench capacitor forming process. According to the present invention, after forming a trench, successive processes become easy and reliability of device can be enhanced.
Inventors
- 👤 Jae kap Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:17
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0385; H10B12/30; H10B12/37; H10B12/373; H10D; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
168 words
A method for fabricating a dynamic random access memory having a trench capacitor, comprising the steps of: forming a trench capacitor on the upper portion of a first semiconductor substrate doped with a first conductive type impurity; forming an insulation layer on the upper portion of the device body having the trench capacitor; attaching a second semiconductor substrate doped with a second conductive type impurity on the upper portion of the insulation layer; exposing a charge storage electrode of the trench capacitor by sequentially patterning the second semiconductor substrate and the insulation layer; forming a strap electrically connected with the charge storage electrode by filling a conductive material to the exposing portion, which is exposed by patterning the second semiconductor substrate and the insulation layer; removing a portion of the second semiconductor substrate and the strap and forming a device separating layer on the removed portion; and forming a transistor on the second semiconductor substrate wherein a drain electrode of the transistor is electrically connected to the strap.
Claim 2
Independent Claim
168 words
A method for fabricating a dynamic random access memory having a trench capacitor, comprising the steps of: forming a trench capacitor on the upper portion of a first semiconductor substrate doped with a first conductive type impurity; forming an insulation layer on the upper portion of the device body having the trench capacitor; attaching a second semiconductor substrate doped with a second conductive type impurity on the upper portion of the insulation layer; exposing a charge storage electrode of the trench capacitor by sequentially patterning the second semiconductor substrate and the insulation layer; forming a strap electrically connected with the charge storage electrode by filling a conductive material to the exposing portion, which is exposed by patterning the second semiconductor substrate and the insulation layer; removing a portion of the second semiconductor substrate and the strap and forming a device separating layer on the removed portion; and forming a transistor on the second semiconductor substrate wherein a drain electrode of the transistor is electrically connected to the strap.
Claim 3
Dependent Claim
39 words
The method according to claim 1 , wherein the method further comprising the steps of: exposing an align key, which is formed in forming step the trench capacitor to the first semiconductor substrate, after attaching the second semiconductor substrate.
Claim 4
Dependent Claim
32 words
The method according to claim 1 , wherein the strap is formed to be electrically connected with a drain electrode of the transistor after forming a transistor on the second semiconductor substrate.
Claim 5
Dependent Claim
27 words
The method according to claim 3 , wherein the strap is formed with silicon which is doped with a first conductive type impurity having a high concentration.
Claim 6
Dependent Claim
27 words
The method according to claim 1 , wherein the first conductive type impurity is an n-type impurity and the second conductive type impurity is a p-type impurity.
Claim 7
Dependent Claim
91 words
The method according to claim 1 , wherein an alignment method when attaching the first and second semiconductor substrates comprising the steps of: forming an align key on the upper portion of the first semiconductor substrate; attaching the second semiconductor substrate to the upper portion of the first semiconductor substrate; exposing the align key on the first semiconductor substrate by etching the second semiconductor substrate; and aligning a transistor by the align key of the first semiconductor substrate when forming the transistor on the upper portion of the second semiconductor substrate.
Claim 8
Dependent Claim
26 words
The method according to claim 6 , wherein the align key is a trench capacitor being formed at the scribe line on the first semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-02-09 | 2007-08-11 | 2008-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-02-09 | 2011-08-11 | 2012-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-02-09 | 2015-08-11 | 2016-02-10 | $7700.00 | Window Closed / Lapsed |