US6735104B2
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US
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Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
Assignee: SanDisk Technologies LLC
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Filing: 2003-05-16
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Granted: 2004-05-11
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Expires: 2023-05-16
Abstract
Abstract The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
Inventors
- 👤 Roy E. Scheuerlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:15
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C17/00; G11C17/14; G11C17/18; G11C5/00; G11C5/02; G11C5/025; G11C7/00; G11C7/06; G11C7/062; G11C7/067; G11C7/18; G11C8/08; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 64
Claim 1
Independent Claim
78 words
A memory device comprising: a plurality of memory arrays comprising a first memory array and a second memory array; a first circuit structure disposed beneath the first memory array, wherein the first circuit structure comprises all of the circuits disposed beneath the first memory array; and a second circuit structure, different from the first circuit structure, disposed beneath the second memory array, wherein the second circuit structure comprises all of the circuits disposed beneath the second memory array.
Claim 2
Dependent Claim
78 words
A memory device comprising: a plurality of memory arrays comprising a first memory array and a second memory array; a first circuit structure disposed beneath the first memory array, wherein the first circuit structure comprises all of the circuits disposed beneath the first memory array; and a second circuit structure, different from the first circuit structure, disposed beneath the second memory array, wherein the second circuit structure comprises all of the circuits disposed beneath the second memory array.
Claim 3
Dependent Claim
19 words
The memory device of claim 1 , wherein the first circuit structure includes at least one row decoder circuit.
Claim 4
Dependent Claim
19 words
The memory device of claim 2 , wherein the second circuit structure includes at least one column decoder circuit.
Claim 5
Dependent Claim
18 words
The memory device of claim 2 , wherein the first circuit structure includes a second row decoder circuit.
Claim 6
Dependent Claim
19 words
The memory device of claim 1 , wherein the second circuit structure includes at least one column decoder circuit.
Claim 7
Dependent Claim
19 words
The memory device of claim 5 , wherein the first circuit structure includes at least one row decoder circuit.
Claim 8
Dependent Claim
18 words
The memory device of claim 5 , wherein the second circuit structure includes a second column decoder circuit.
Claim 9
Dependent Claim
56 words
The memory device of claim 1 , wherein the plurality of memory arrays comprise first and second sets of memory arrays, wherein the first circuit structure is disposed beneath each of the memory arrays in the first set, and wherein the second circuit structure is disposed beneath each of the memory arrays in the second set.
Claim 10
Dependent Claim
40 words
A memory device comprising: a plurality of memory arrays disposed above a substrate; a first decoder circuit associated with and largely disposed beneath a first memory array and also associated with a second memory array; and a second decoder circuit.
Claim 11
Dependent Claim
40 words
A memory device comprising: a plurality of memory arrays disposed above a substrate; a first decoder circuit associated with and largely disposed beneath a first memory array and also associated with a second memory array; and a second decoder circuit.
Claim 12
Dependent Claim
19 words
The memory device of claim 9 , wherein the second memory array is adjacent to the first memory array.
Claim 13
Dependent Claim
32 words
The memory device of claim 9 , wherein the second decoder circuit is associated with and largely disposed beneath the first memory array and is also associated with a third memory array.
Claim 14
Dependent Claim
19 words
The memory device of claim 11 , wherein the third memory array is adjacent to the first memory array.
Claim 15
Dependent Claim
33 words
The memory device of claim 9 further comprising a third decoder circuit associated with and largely disposed beneath a fourth memory array, said third decoder circuit also associated with the first memory array.
Claim 16
Dependent Claim
19 words
The memory device of claim 13 , wherein the fourth memory array is adjacent to the first memory array.
Claim 17
Dependent Claim
33 words
The memory device of claim 13 further comprising a fourth decoder circuit associated with and largely disposed beneath a fifth memory array, said fourth decoder circuit also associated with the first memory array.
Claim 18
Dependent Claim
19 words
The memory device of claim 15 , wherein the fifth memory array is adjacent to the first memory array.
Claim 19
Dependent Claim
34 words
The memory device of claim 9 further comprising a group of array line driver circuits associated with the first decoder circuit, said group associated with the first memory array and the second memory array.
Claim 20
Dependent Claim
41 words
The memory device of claim 9 further comprising two groups of array line driver circuits associated with the first decoder circuit, one such group associated with the first memory array and the other such group associated with the second memory array.
Claim 21
Dependent Claim
17 words
The memory device of claim 9 , wherein the first decoder circuit comprises a column decoder circuit.
Claim 22
Dependent Claim
17 words
The memory device of claim 9 , wherein the first decoder circuit comprises a row decoder circuit.
Claim 23
Dependent Claim
61 words
The memory device of claim 20 , wherein the row decoder circuit further comprises a first group of word line driver circuits associated with word lines within the first memory array and a second group of word line driver circuits associated with word lines within the second memory array, whereby word lines are discontinuous between the first and second memory arrays.
Claim 24
Dependent Claim
22 words
The memory device of claim 9 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays.
Claim 25
Dependent Claim
69 words
The memory device of claim 11 wherein the first memory array comprises first and second sets of array lines of like kind, wherein the first set of array lines is associated with the first decoder circuit and the second set of array lines is associated with the second decoder circuit, and wherein the array lines of the first set are interleaved with the array lines of the second set.
Claim 26
Dependent Claim
30 words
The memory device of claim 23 wherein the first set of array lines and the second set of array lines are driven from opposites sides of the first memory array.
Claim 27
Dependent Claim
49 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein at least one of the plurality of row or column decoder circuits is associated with a memory array above its location and an adjacent memory array.
Claim 28
Dependent Claim
49 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein at least one of the plurality of row or column decoder circuits is associated with a memory array above its location and an adjacent memory array.
Claim 29
Dependent Claim
56 words
The memory device of claim 25 , wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array; and further comprising only one set of word line drivers between adjacent memory arrays, whereby word lines are continuous between said adjacent memory arrays.
Claim 30
Dependent Claim
56 words
The memory device of claim 25 , wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array; and further comprising two sets of word line drivers between adjacent memory arrays, whereby word lines are not continuous between said adjacent memory arrays.
Claim 31
Dependent Claim
56 words
The memory device of claim 25 , wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array; and further comprising only one set of bit line drivers between adjacent memory arrays, whereby bit lines are continuous between said adjacent memory arrays.
Claim 32
Dependent Claim
56 words
The memory device of claim 25 , wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array; and further comprising two sets of bit line drivers between adjacent memory arrays, whereby bit lines are not continuous between said adjacent memory arrays.
Claim 33
Dependent Claim
39 words
The memory device of claim 25 , wherein at least one row decoder circuit comprises a plurality of word line decoders, and wherein at least one word line decoder is connected to control an associated plurality of word lines.
Claim 34
Dependent Claim
24 words
The memory device of claim 30 wherein said at least one word line decoder is coupled to an associated plurality of word line drivers.
Claim 35
Dependent Claim
27 words
The memory device of claim 31 wherein each word line driver comprises a switch device arranged to couple the respective word line to an associated bias line.
Claim 36
Dependent Claim
28 words
The memory device of claim 31 wherein each word line driver comprises two devices arranged to couple the respective word line to either of two associated bias lines.
Claim 37
Dependent Claim
22 words
The memory device of claim 25 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays.
Claim 38
Dependent Claim
75 words
The memory device of claim 25 wherein a first memory array of said plurality of memory arrays comprises first and second sets of array lines of like kind, wherein the first set of array lines is associated with a first decoder circuit, and the second set of array lines is associated with a second decoder circuit, and wherein the array lines of the first set are interleaved with the array lines of the second set.
Claim 39
Dependent Claim
30 words
The memory device of claim 35 wherein the first set of array lines and the second set of array lines are driven from opposites sides of the first memory array.
Claim 40
Dependent Claim
23 words
The memory device of claim 35 wherein the first decoder circuit and the second decoder circuit are disposed beneath the first memory array.
Claim 41
Dependent Claim
20 words
The memory device of claim 25 , wherein the plurality of memory arrays comprise a plurality of semiconductor-based memory cells.
Claim 42
Dependent Claim
20 words
The memory device of claim 25 , wherein the plurality of memory arrays comprise a plurality of anti-fuse memory cells.
Claim 43
Dependent Claim
20 words
The memory device of claim 25 , wherein the plurality of memory arrays comprise a plurality of write-once memory cells.
Claim 44
Dependent Claim
23 words
The memory device of claim 25 , wherein the plurality of memory arrays comprise memory cells formed at least in part by railstacks.
Claim 45
Dependent Claim
95 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 46
Dependent Claim
95 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 47
Dependent Claim
95 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 48
Dependent Claim
95 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 49
Dependent Claim
123 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 50
Dependent Claim
123 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 51
Dependent Claim
104 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 52
Dependent Claim
104 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 53
Dependent Claim
104 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 54
Dependent Claim
104 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides; wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
Claim 55
Dependent Claim
90 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 56
Dependent Claim
90 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 57
Dependent Claim
90 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 58
Dependent Claim
90 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 59
Dependent Claim
118 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 60
Dependent Claim
118 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 61
Dependent Claim
99 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 62
Dependent Claim
99 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 63
Dependent Claim
99 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
Claim 64
Dependent Claim
99 words
A memory device comprising: a plurality of memory arrays; a plurality of row decoder circuits; and a plurality of column decoder circuits; wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides; wherein the memory cells of the plurality of memory arrays comprise one of the following: a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-05-11 | 2007-11-10 | 2008-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-11 | 2011-11-10 | 2012-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-11 | 2015-11-10 | 2016-05-11 | $7700.00 | Window Closed / Lapsed |