Patent US6882557B2 successfully refreshed from Google Patents.
US6882557B2
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Semiconductor memory device
Assignee: Longitude Semiconductor SARL
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Filing: 2003-09-05
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Granted: 2005-04-19
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Expires: 2023-09-05
Abstract
Abstract The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased. The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.
Inventors
- 👤 Kazuhiko Kajigaya
- 👤 Hiromasa Noda
- 👤 Shinichi Miyatake
- 👤 Riichiro Takemura
- 👤 Tomonori Sekiguchi
- 👤 Takeshi Sakata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C29/00; G11C29/04; G11C29/50; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18; H; H10; H10B; H10B12/00; H10B12/30; H10B12/48; H10D; H10D89/00; H10D89/10; G11C2207/00; G11C2207/005; G11C2211/00; G11C2211/401; G11C2211/4013; H10B12/50
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
227 words
A semiconductor memory device comprises: a memory array having plurality of word-lines arranged in a predetermined direction and in parallel to each other, a plurality of bit lines arranged orthogonally to a plurality of the word-lines and in parallel to each other, and a plurality of memory cells arranged at predetermined intersection points of a plurality of the word-lines and a plurality of the bit-lines, the number of the predetermined intersection points being equal to half of all the intersection points; a plurality of switches connected to one-side end of the bit-lines provided at an odd-numbered position of a plurality of the bit-lines and connected to the other-side end of the bit-line provided at an even-numbered position, respectively; and a plurality of unit circuits each having two terminal connected to a pair of odd-numbered or even-numbered bit lines of a plurality of the bit lines, the unit circuits being arranged in a column in a predetermined direction in the vicinities to the both ends of a plurality of the bit lies, respectively, the predetermined intersection points being determined in such a manner that when one of a plurality of the word lines is selected, the memory cells of a plurality of the memory cells connected to the selected word line can be electrically connected, one by one, to the terminals of a plurality of the unit circuit.
Claim 2
Dependent Claim
227 words
A semiconductor memory device comprises: a memory array having plurality of word-lines arranged in a predetermined direction and in parallel to each other, a plurality of bit lines arranged orthogonally to a plurality of the word-lines and in parallel to each other, and a plurality of memory cells arranged at predetermined intersection points of a plurality of the word-lines and a plurality of the bit-lines, the number of the predetermined intersection points being equal to half of all the intersection points; a plurality of switches connected to one-side end of the bit-lines provided at an odd-numbered position of a plurality of the bit-lines and connected to the other-side end of the bit-line provided at an even-numbered position, respectively; and a plurality of unit circuits each having two terminal connected to a pair of odd-numbered or even-numbered bit lines of a plurality of the bit lines, the unit circuits being arranged in a column in a predetermined direction in the vicinities to the both ends of a plurality of the bit lies, respectively, the predetermined intersection points being determined in such a manner that when one of a plurality of the word lines is selected, the memory cells of a plurality of the memory cells connected to the selected word line can be electrically connected, one by one, to the terminals of a plurality of the unit circuit.
Claim 3
Dependent Claim
46 words
A semiconductor memory device according to claim 1 , wherein when one of a plurality of the word lines is selected, the switches operates so that the memory cells connected to the selected word line are electrically connected to the terminals of the unit circuits, respectively.
Claim 4
Dependent Claim
29 words
A semiconductor memory device according to claim 1 , wherein a plurality of the switches are MOS transistor switches in which two switches are integrated with each other, respectively.
Claim 5
Dependent Claim
80 words
A semiconductor memory device according to claim 3 , wherein each MOS transistor switch contains two gate electrodes arranged in parallel to each other, two drain regions formed on both sides of the gate electrodes, independently from each other, and a single source region formed between the two gate electrodes, a pair of the odd-numbered or even-numbered bit lines are connected to the two drain regions, respectively, and a terminal of each unit circuit is connected to the source region.
Claim 6
Dependent Claim
21 words
A semiconductor memory device according to claim 1 , wherein each memory cell comprises one cell-use MOS transistor and one capacitor.
Claim 7
Dependent Claim
37 words
A semiconductor memory device according to claim 5 , wherein the cell-use MOS transistor is formed on a substrate doped into a p-type, and contains as a gate electrode a polySi layer doped with a p-type impurity.
Claim 8
Dependent Claim
69 words
A semiconductor memory device according to claim 6 , wherein each unit circuit contains a first MOS transistor which is formed on a substrate doped into a p-type and has a first polySi layer doped with a n-type impurity, and a second MOS transistor which is formed on a substrate doped into a n-type and has as a gate electrode a second polySi layer doped with a p-type impurity.
Claim 9
Dependent Claim
88 words
A semiconductor memory device according to claim 6 , further comprising a peripheral circuit for controlling the cell array and a plurality of the switches, the peripheral circuit containing a first MOS transistor which is formed on a substrate doped into a p-type, and has as a gate electrode a first polySi layer doped with an n-type impurity, and a second MOS transistor which is formed on a substrate doped into an n-type, and has as a gate electrode a second polySi layer doped with an p-type impurity.
Claim 10
Dependent Claim
51 words
A semiconductor memory device according to claim 5 , wherein each word line comprises a first wiring layer using for the gate electrode of the cell-use MOS transistor and a second wiring layer having a lower resistance than the first wiring layer and backing the first wiring layer at predetermined positions.
Claim 11
Dependent Claim
57 words
A semiconductor memory device according to claim 5 , wherein each word line comprises a first wiring layer using for the gate electrode of the cell-use MOS transistor, a drive circuit for driving the first wiring layer, and a second wiring layer connected to the drive circuit and having a lower resistance than the first wiring layer.
Claim 12
Dependent Claim
38 words
A semiconductor memory device according to claim 1 , wherein the unit circuits are connected, in addition to the above-described memory cell array, to another memory cell array having the same constitution as the above-described memory cell array.
Claim 13
Dependent Claim
36 words
A method of testing the semiconductor memory device defined in claim 1 comprising the step of: selecting a plurality of the word lines sequentially one by one, and turning-on all of a plurality of the switches.
Claim 14
Dependent Claim
98 words
A method of testing the semiconductor memory device defined in claim 1 comprising the steps of; selecting a plurality of the word lines sequentially one by one, and controlling a plurality of the switches so that the memory cell is electrically connected to only one terminal of each of a plurality of the unit circuits: and thereafter, again, selecting a plurality of the word lines sequentially one by one, and controlling a plurality of the switches so that the memory cell is electrically connected to only the other terminal of each of a plurality of the unit circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-04-18 | 2008-10-18 | 2009-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-04-18 | 2012-10-18 | 2013-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-04-18 | 2016-10-18 | 2017-04-19 | $7700.00 | Window Closed / Lapsed |