Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device

Claim 2

A program storage medium that stores a development method for developing integrated circuits, the development method comprising: a core generating including generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, by a unit that selects optional blocks having a connection to group the blocks, wherein the core (logic core) in the HDL format includes an optional number of blocks of ports, the blocks having optional size and port connection information; creating a temporary chip design from chip terminal information by using the logic synthesis tool to generate a terminal in the temporary chip design; a design generating including generating a design identical to that created at the creating, as a cell within the design created; connecting a chip design port with a cell port, wherein a name of the design port is identical to a name of the cell port; inserting an I/O buffer, depending on a device technology, into a net between the connected chip design port and the cell port; and a netlist generating/expanding including generating a netlist by replacing the cell by the core (logic core) created at the core generating, and expanding a hierarchy of the design created at the design generating, being the top hierarchy.

Claim 3

The program storage medium according to claim 1 , wherein in the development method, the core generating further includes creating a netlist, including an optional number of blocks of ports, the blocks having optional size and port connection information, from the ASIC core (logic core) made of ports of blocks and port connection information, by the unit that selects the optional blocks having the connection to group the blocks.

Claim 4

A development method for developing integrated circuits, to be used when concurrent development of an ASIC and a programmable logic device is conducted, comprising: a core generating including generating a core (logic core) including an optional number of blocks of ports, the blocks having optional size and port connection information, from a netlist referred to as an ASIC core (logic core) made of ports of blocks and port connection information, by a unit that selects optional blocks having a connection to group the blocks; creating a temporary chip design from chip terminal information by using a logic synthesis tool; a terminal generating including generating a terminal, with a name existing in the chip terminal information, in the temporary chip design; a design generating including generating a design identical to that created at the creating, as a cell within the design created; connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port; inserting an I/O buffer, depending on a device technology, from the chip terminal information into a connection net; replacing the cell by the core (logic core) created at the core generating; and a chip netlist generating including generating a chip netlist by expanding a hierarchy of the temporary chip design created at the creating, being the top hierarchy of the core (logic core) in the HDL format.

Claim 5

A development method for developing integrated circuits, to be used when concurrent development of an ASIC and a programmable logic device is conducted, comprising: a core generating including generating a core (logic core) including an optional number of blocks of ports, the blocks having optional size and port connection information, from a netlist referred to as an ASIC core (logic core) made of ports of blocks and port connection information, by a unit that selects optional blocks having a connection to group the blocks; creating a temporary chip design from chip terminal information by using a logic synthesis tool; a terminal generating including generating a terminal, with a name existing in the chip terminal information, in the temporary chip design; a design generating including generating a design identical to that created at the creating, as a cell within the design created; connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port; inserting an I/O buffer, depending on a device technology, from the chip terminal information into a connection net; replacing the cell by the core (logic core) created at the core generating; and a chip netlist generating including generating a chip netlist by expanding a hierarchy of the temporary chip design created at the creating, being the top hierarchy of the core (logic core) in the HDL format.

Claim 6

The development method of integrated circuits according to claim 3 , wherein when a netlist including an optional number of blocks of ports, the blocks having optional size and port connection information is created, a port name in the top hierarchy, being a net name, is corrected to match with a port name of a block to be connected, thereby creating a netlist made of ports of blocks and port connection information.

Claim 7

A program storage medium that records a development method for developing integrated circuits, the development method comprising: a core generating including generating a core (logic core) including an optional number of blocks of ports, the blocks having optional size and port connection information, from an ASIC core (logic core) made of ports of blocks and port connection information, by a unit that selects optional blocks having a connection to group the blocks; creating a temporary chip design from chip terminal information by using a logic synthesis tool to generate a terminal, with a name existing in the chip terminal information, in the temporary chip design; a design generating including generating a design identical to that created at the creating, as a cell within the design created; connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port; inserting an I/O buffer, depending on a device technology, from the chip terminal information into a connection net; replacing the cell by the core (logic core) created at the core generating; and a chip netlist generating including generating a chip netlist by expanding a hierarchy of the temporary chip design created at the creating, being the top hierarchy of the core (logic core) in the HDL format.

Claim 8

A program storage medium that records a development method for developing integrated circuits, the development method comprising: a core generating including generating a core (logic core) including an optional number of blocks of ports, the blocks having optional size and port connection information, from an ASIC core (logic core) made of ports of blocks and port connection information, by a unit that selects optional blocks having a connection to group the blocks; creating a temporary chip design from chip terminal information by using a logic synthesis tool to generate a terminal, with a name existing in the chip terminal information, in the temporary chip design; a design generating including generating a design identical to that created at the creating, as a cell within the design created; connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port; inserting an I/O buffer, depending on a device technology, from the chip terminal information into a connection net; replacing the cell by the core (logic core) created at the core generating; and a chip netlist generating including generating a chip netlist by expanding a hierarchy of the temporary chip design created at the creating, being the top hierarchy of the core (logic core) in the HDL format.