Demand assigned multiple access (DAMA) device controller interface

Claim 1

A controller interface for a demand assigned multiple access (DAMA) device comprising: a matched pair of first-in, first-out (FIFO) memory devices, said matched pair consisting of a receive FIFO and a transmit FIFO, said receive FIFO being controlled by a clock signal output by said DAMA device, wherein serial format data is input into said receive FIFO which outputs parallel format data onto a first internal parallel data bus internal to said controller interface, and wherein parallel format data from a second parallel data bus internal to said controller interface is input into said transmit FIFO which outputs serial format data; first buffer means for receiving parallel format data from said first internal parallel data bus and for outputting same onto an external parallel control data bus external to said controller interface; second buffer means for receiving parallel format data from said external parallel control data bus and for outputting same onto said second internal parallel data bus; third buffer means for storing status information from said receive FIFO indicative of the presence or absence of data stored within said receive FIFO, and for storing status information from said transmit FIFO indicative of said transmit FIFO's readiness to accept data; control means for issuing an enable signal based on said status information to enable said receive and transmit FIFOs wherein said receive FIFO outputs parallel data onto said first internal parallel data bus when enabled, and wherein said transmit FIFO outputs serial format data when enabled; and clocking means for clocking data through said transmit FIFO, said clocking means generating clock pulses at a rate that is approximately equivalent to that of said clock signal used to control said receive FIFO.

Claim 5

An apparatus for controlling a plurality of demand assigned multiple access (DAMA) devices comprising: processing means for processing DAMA control data; a control data bus for transmitting said DAMA control data to and from said processing means in parallel format; a plurality of matched pairs of first-in, first-out (FIFO) memory devices, one matched pair corresponding to each DAMA device with each DAMA device having an operative clock rate, each matched pair consisting of a receive FIFO and a transmit FIFO, said receive FIFO being controlled at said operative clock rate of said corresponding DAMA device, wherein serial format data is input into said receive FIFOs which output parallel format data onto a first parallel data bus, and wherein parallel format data from a second parallel data bus is input into said transmit FIFOs which output serial format data; first buffer means for receiving parallel format data on said first parallel data bus and for outputting same onto said control data bus; second buffer means for receiving parallel format data on said control data bus and outputting same onto said second parallel data bus; third buffer means for storing status information from each of said receive FIFOs indicative of the presence or absence of data stored within said receive FIFOs, and for storing status information from each of said transmit FIFOs indicative of said transmit FIFOs' readiness to accept data; control means for issuing an enable signal based on said status information to enable a selected one of said receive and transmit FIFOs wherein said selected receive FIFO outputs parallel data onto said first parallel data bus, and wherein said selected transmit FIFO outputs serial format data; and clocking means for clocking data through said selected transmit FIFOs, said clocking means generating clock pulses at a rate that is approximately equivalent to said corresponding DAMA devices' operative clock rate.

Claim 6

An apparatus for controlling a plurality of demand assigned multiple access (DAMA) devices comprising: processing means for processing DAMA control data; a control data bus for transmitting said DAMA control data to and from said processing means in parallel format; a plurality of matched pairs of first-in, first-out (FIFO) memory devices, one matched pair corresponding to each DAMA device with each DAMA device having an operative clock rate, each matched pair consisting of a receive FIFO and a transmit FIFO, said receive FIFO being controlled at said operative clock rate of said corresponding DAMA device, wherein serial format data is input into said receive FIFOs which output parallel format data onto a first parallel data bus, and wherein parallel format data from a second parallel data bus is input into said transmit FIFOs which output serial format data; first buffer means for receiving parallel format data on said first parallel data bus and for outputting same onto said control data bus; second buffer means for receiving parallel format data on said control data bus and outputting same onto said second parallel data bus; third buffer means for storing status information from each of said receive FIFOs indicative of the presence or absence of data stored within said receive FIFOs, and for storing status information from each of said transmit FIFOs indicative of said transmit FIFOs' readiness to accept data; control means for issuing an enable signal based on said status information to enable a selected one of said receive and transmit FIFOs wherein said selected receive FIFO outputs parallel data onto said first parallel data bus, and wherein said selected transmit FIFO outputs serial format data; and clocking means for clocking data through said selected transmit FIFOs, said clocking means generating clock pulses at a rate that is approximately equivalent to said corresponding DAMA devices' operative clock rate.